MT90220
Table of Contents
3.3.7 Rate Recovery ................................................................................................................................. 19
3.3.8 Cell Buffer/RAM Controller............................................................................................................... 19
3.3.9 Cell Sequence Recovery ................................................................................................................. 19
3.3.10 Delay Between Links ....................................................................................................................... 20
3.3.10.1 RX Recombiner Delay Value .................................................................................................... 20
3.3.10.2 RX Maximum Operational Delay Value..................................................................................... 20
3.3.10.3 Link Out of Delay Synchronization (LODS)............................................................................... 20
3.3.10.4 Negative Delay Values.............................................................................................................. 21
3.3.10.5 Measured Delay Between Links................................................................................................ 21
3.3.10.6 Incrementing/Decrementing the Recombiner Delay ................................................................. 21
3.3.11 RX IMA Group Start-Up ...................................................................................................................21
3.3.12 Link Addition .................................................................................................................................... 22
3.3.13 Link Deletion .................................................................................................................................... 22
3.3.14 Disabling an IMA Group................................................................................................................... 22
3.4 The ATM Receive Path in UNI ................................................................................................................. 22
4.0 Description of the PCM Interface................................................................................................................ 23
4.1 Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters................................................................ 23
4.2 PCM System Interface Modes.................................................................................................................. 24
4.2.1 Mode 2 and 6: ST-BUS Interface for T1 .......................................................................................... 25
4.2.1.1 Detailed ST-BUS Spaced Mapping (3 of Every 4 Channels).................................................... 26
4.2.1.2 Detailed ST-BUS Grouped Mapping (24 Consecutive Channels)............................................. 26
4.2.1.3 Detailed ST-BUS ISDN Mapping (T1 ISDN Modes) ................................................................. 26
4.2.2 Mode 4 and 8: ST-BUS lnterface for E1 .......................................................................................... 26
4.2.3 Mode 1 and 5: Generic PCM Interface for T1.................................................................................. 26
4.2.3.1 1.544 MHz Clock....................................................................................................................... 27
4.2.3.2 2.048 MHz Clock....................................................................................................................... 27
4.2.4 Mode 3 and 7: Generic PCM Interface for E1.................................................................................. 27
4.2.5 TXSYNC Signal in Mode 5 and 7..................................................................................................... 28
4.3 Clocking Options ...................................................................................................................................... 28
4.3.1 Verification of the RXSYNC Period.................................................................................................. 28
4.3.2 Verification of the TXSYNC Period .................................................................................................. 28
4.3.3 Primary and Secondary Reference Signals..................................................................................... 28
4.3.4 Verification of Clock Activity............................................................................................................. 30
4.3.5 Clock Selection ................................................................................................................................ 30
5.0 UTOPIA Interface Operation........................................................................................................................ 30
5.1 ATM Input Port ......................................................................................................................................... 30
5.2 ATM Output Port ...................................................................................................................................... 31
5.3 UTOPIA Operation With a Single PHY..................................................................................................... 31
5.4 UTOPIA Operation with Multiple PHY...................................................................................................... 31
5.5 UTOPIA Operation in UNI Mode .............................................................................................................. 31
5.6 UTOPIA Operation in IMA Mode.............................................................................................................. 32
5.7 Examples of UTOPIA Operation Modes................................................................................................... 32
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