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MT90220 参数 Datasheet PDF下载

MT90220图片预览
型号: MT90220
PDF下载: 下载PDF文件 查看货源
内容描述: 八IMA / UNI PHY设备 [Octal IMA/UNI PHY Device]
分类和应用:
文件页数/大小: 116 页 / 305 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT90220  
reported in the TX IMA Mode Status register. It  
then can be assigned to another IMA group.  
ATM User cells are transferred from the Input  
UTOPIA port to the TX PCM port.  
When removing the last link of a TX IMA group, the  
TX Utopia FIFO has to be empty. This can easily be  
done by first disabling the source of ATM cells (ATM  
Utopia contoller), then disabling the TX Utopia Port  
using the UTOPIA input Link or Group PHY enable  
registers while still keeping the "Send User Cell" bit  
of the TX Link Control Centre register set to 1. The  
level of the TX Utopia FIFO can be monitored using  
TX Utopia FIFO Level register. The above  
procedure can then be applied to assign the link in  
UNI mode.  
3.0 The ATM Receive Path  
The receive path corresponds to the cell flow from  
the T1/E1 interfaces to the ATM UTOPIA Interface.  
The MT90220 provides cell delineation and optional  
cell filtering to discard Unassigned or Idle cells on  
each link. The incoming cells are stored in the  
external RAM required in IMA mode to perform cell  
recovery due to delay variation between the links  
introduced by the network.  
3.1 Cell Delineation Function  
When the link is configured in UNI mode, IDLE cells  
are transmitted. Writing to the TX PCM Link Control  
registers either turns off the transmitter or  
reconfigures the link into another mode.  
This block provides the circuitry necessary to  
perform functions such as Cell Delineation (CD), cell  
payload de-scrambling, HEC verification and filtering  
of Idle (UNI) cells. The CD circuit delineates ATM  
cells received from the payload of the T1 or E1 frame  
through the PCM Interface.  
2.5 ATM Transmit Path in UNI Mode  
A maximum of eight independent T1/E1 interfaces  
can be selected in UNI mode. Figure 4 gives a  
functional block diagram of the transmitter in UNI  
mode.  
When performing delineation, correct HEC  
calculations are interpreted to indicate cell  
boundaries. The CD circuit performs a sequential  
byte by byte hunt for a correct HEC sequence. While  
performing this hunt, the cell delineation state  
machine is in the HUNT state. Figure 5 depicts a  
state diagram of the cell delineation operation.  
ATM cells received from the ATM port are placed in a  
TX UTOPIA FIFO, waiting to be transmitted. If the  
Idle/Unassigned cell removal option is selected,  
these cells are dropped. If the TX UTOPIA FIFO is  
empty, an Idle cell is sent to the output link. The  
content of the Idle cell is pre-initialized with the  
header bytes set at 0x00, 0x00, 0x00 and 0x01. The  
payload bytes are set to 0x6A.  
Correct HEC (byte by byte)  
Incorrect HEC  
(cell by cell)  
HUNT  
PRESYNC  
TX UTOPIA FIFO Length Definition registers are  
used to set the TX UTOPIA FIFO size. The total  
number of cells in all the TX UTOPIA FIFOs and TX  
Link FIFO (includes the links used in IMA Mode and  
the links used in UNI Mode) is limited to 58.  
ALPHA  
Consecutive  
Incorrect HEC  
(cell by cell)  
DELTA Consecutive  
Correct HEC  
SYNC  
(cell by cell)  
Figure 5 - Cell Delineation State Diagram  
When a correct HEC is found, the CD circuit locks on  
the cell boundary and enters the PRESYNC state.  
The PRESYNC state keeps checking the HEC to  
ensure that the previous indication was not false.  
Idle Cells are transmitted on the UNI PCM Interface  
until the bit corresponding to the link in the UTOPIA  
Input Link PHY Enable register is set. Then, the  
ATM CELL DELINEATION SYNC STATE  
ALPHA  
Consecutive  
Incorrect HCS’s  
Jump to HUNT  
State  
Cell  
Cell  
Accepted  
Discarded  
DELTA  
Consecutive  
Correct HCS’s  
(PRESYNC State)  
HCS Multi-Bit Error Detected (cell discarded)  
HCS Single Bit Error Detected (corrected or dropped)  
No HCS Errors Detected  
Correction  
Detection  
Figure 6 - SYNC State Block Diagram  
15  
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