MT90220
22
22
30
30
30
31
34
34
38
42
45
47
47
51
60
62
75
79
21
22
29
30
30
31
32
32
37
41
44
46
46
51
59
61
73
77
Replaced:
Replaced:
Replaced:
Inserted:
Replaced:
Inserted:
Replaced:
Replaced:
Replaced:
Replaced:
Replaced:
Replaced:
Replaced:
Inserted:
“decreases” With: “decreases or”
“5 ” With: “6 ”
“used.” With: “used for any MT90220 port.”
“The cell available satus line (…”
“port. ” With: “port in MPHY mode. ”
“In this mode, the bit …”
“information:” With: “information and are active as …”
“link” With: “link, , with good or bad …”
“0EB” With: “0EF”
“ho ” With: “no ”
“Hex):” With: “Bin):”
“mode ” With: “mode (adaptive) algorithm ”
“mode ” With: “mode (fixed) algorithm”
"By the MT90220... in Cell Byte #14
“Write 01 ” With: “Write 00”
“Hex):” With: “Bin):”
"This bit is set... to Bit #5
"General Status register" with "General Status and Test
Register
Replaced:
Replaced:
Inserted:
Replaced:
90
93
93
93
94
94
94
99
99
99
99
90
91
91
91
92
92
92
97
97
97
97
Updated:
Replaced:
Removed:
Figure 27
“2 ” With: “1 ”
2nd line of table
Figure updated for 2 clock cycles access time
Replaced:
Removed:
“2 ” With: “1 ”
2nd line of table
Figure updated for 2 clock cycles access time
Replaced:
Replaced:
Replaced:
Replaced:
“10” With: “5”
“10” With: “5”
“10 CLK period” With: “10”
“ns” With: “clk period”
103