Preliminary Information
Pin Description (continued)
Pin
31
Name
SCLK
Description
MT90210
Serial Port Clock (input).
The SCLK clock is used to control the serial port operation in
modes 1,2,3 and 4. Depending on the operation mode selected at the MD0-MD2 inputs,
this input can accept 4.096 (MD2-0=000), 8.192 (MD2-0=001) or 16.384 (MD2-0 =010 and
011) MHz clock. In mode 5, this input is ignored.
H-MVIP C4.
This is a 4.096 MHz clock utilized in modes 4 and 5 to maintain compatibility
with existing MVIP-90 systems. It is utilized to sample the frame pulse input (F0i). Not used
in Modes 1 - 3.
Boundary Scan Test Data Input.
Boundary Scan Test Mode Select.
Boundary Scan Test Clock.
Boundary Scan Test Reset.
Frame Synchronization Signal (TTL compatible input).
This input signal establishes
the frame boundary for the serial input/output streams.
32
HC4
33
34
35
36
37
38-40
TDI
TMS
TCK
TRST
F0i
MD2-MD0
Operation Mode Bits 0-2 (Input).
Selects the data rate for the time division, multiplexed
serial streams. 2.048 (mode 1, MD2-0=000), 4.096 (mode 2, MD2-0=001) or 8.192 (mode
3, MD2-0=010) Mb/s data rates are available. When MD2-0 are set to 011 (mode 4), the
MT90210 operates in mixed data rates mode where S16-23 operate at 8.192 Mb/s and the
remaining serial streams run at 2.048 Mb/s. In mode 5 (MD2-0=100), the MT90210
operates as per mode 4 but the device will accept a differential clock reference at 16.384
MHz at pins C16+ and C16-.
C16+
C16-
TD
IDDTN
PLLVSS
LP2
LP1
Serial Port Clock Input.
In mode 5 (MD2-0= 100), this is a 16.384 MHz differential signal.
Note used in Modes 1 - 3.
Serial Port Clock Input.
The complement to C16+.
Reserved
- Do not connect.
Connect to Ground.
PLL Ground Input.
Loop Filter Input.
An external RC circuit is required at this input, refer to Figure 10.
Loop Filter Input.
An external RC circuit is required at this input, refer to Figure 10.
42
43
45
46
47
48
49
50
51
52
53
54
PLLAGND
PLL Analog Ground output.
Provides ground to PLL loop filter, refer to Figure 10.
PLLVDD
RST
PCLK
CKout
PLL Power Input.
+5V
RESET.
A low on this pin resets the device.
Parallel Port Clock Input.
CKout must be connected to this input.
Internal VCO Output Signal.
Output of internal PLL frequency multiplier. In mode 1 the
frequency is 16.384 MHz, for the other modes the frequency is 32.768 MHz. Must be
connected to PCLK only.
Read/Write Output 1.
This output signal toggles low for the last half of a memory write
cycle indicating valid data.
Read/Write Output 2.
This output is low for memory read operations and high for memory
write operations.
56
57
R/W1
R/W2
2-147
MITEL [ MITEL NETWORKS CORPORATION ]
