MT90210
Preliminary Information
PLLAGND
C1
R2
LP1
C2
R1
LP2
R1= 3kΩ
R2= 100Ω + 5%
C1= 10nF + 5%
C2= 20pF
Figure 10 - Analog PLL Low Pass Filter Circuit
PLL Considerations
+5V
The MT90210 device contains an analog Phase-
Locked Loop (PLL) which is used to create a higher
speed clock for parallel port operation from the input
SCLK. This analog PLL requires a loop filter circuit to
be connected to the LP1 and LP2 pins, as shown in
Figure 10. Additionally, the following design
considerations are recommended for the PLL
circuitry:
100Ω
PLLVDD
PLLVSS
1.0nF
Figure 11 - PLLVDD/PLLVSS RC Circuit
•
•
Phase tolerance and jitter are independent of
the PLL frequency.
Jitter is affected by the noise on the PLLVDD
and PLLVSS pins. It will increase if the noise
level increases and is recommended to be kept
less than 10 MHz on PLLVDD.
•
•
•
Use of a C2 capacitor of 15-25pF (+10%) is
recommended to reduce jitter.
The components should be connected within
one inch (1") of the package.
Use a wide PCB trace for PLLVDD and PLLVSS
separate from the device VDD/VSS
connections.
•
In some setups, an RC network (Figure 11)
between PLLVDD and PLLVSS supplies helps
to reduce jitter.
2-156
MITEL [ MITEL NETWORKS CORPORATION ]
