MT89L86
Advance Information
AS/ALE
STi2
STi1
STi0
DTA
CSTo
ODE
STo0
STo1
STo2
STi14/STo8
STi3
STi4
STi5
STi6/A6
STi7/A7
V
DD
FR
CLK
STi8/A0
STi9/A1
STi10/A2
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
IM
STi11/A3
STi12/A4
STi13/A5
DS/RD
R/W/WR
CS
AD7
AD6
AD5
STi15/STo9
STo3
STo4
STo5
STo6/A6
STo7/A7
V
SS
AD0
AD1
AD2
AD3
AD4
V
SS
DTA
STi0
STi1
STi2
AS/ALE
STi3
STi4
STi5
STi6/A6
STi7/A7
V
DD
RESET
FR
CLK
STi8/A0
STi9/A1
STi10/A2
IM
STi11/A3
STi12/A4
STi13/A5
DS/RD
R/W\WR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 PIN SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CSTo
ODE
STo0
STo1
STo2
STi14/STo8
STo3
STo4
STo5
STo6/A6
STo7/A7
V
SS
V
DD
AD0
AD1
AD2
AD3
AD4
STi15/STo9
AD5
AD6
AD7
CS
V
SS
44 PIN PLCC
(JEDEC MO-118, 300mil Wide)
Figure 2 - Pin Connections
Pin Description
Pin #
44
48
PLCC SSOP
2
3-5
7-9
10
2
3-5
7-9
10
Name
Description
DTA
STi0-5
Data Acknowledgment
(Open Drain Output). This active low output indicates that a
data bus transfer is complete. A pull-up resistor is required at this output.
ST-BUS Inputs 0 to 5
(5V-tolerant Inputs). Serial data input streams. These streams
may have data rates of 2.048, 4.096 or 8.192 Mbit/s with 32, 64 or 128 channels,
respectively.
ST-BUS Input 6/Addr.6 input
(5V-tolerant Input). The function of this pin is determined
by the switching configuration enabled. If non-multiplexed CPU bus is used along with
a higher input rate of 8.192 or 4.096 Mb/s, this pin provides A6 address input function.
For 2.048 and 4.096 Mb/s (8x4) applications or when the multiplexed CPU bus
interface is selected, this pin assumes STi6 function. See Control Register bits
description and Tables 1, 2, 6 & 7 for more details.
Note that for applications where both A6 and STi6 inputs are required simultaneously
(e.g., 8 x 4 switching configuration at 4.096 Mb/s or rate conversion between 2.048Mb/
s to 4.196 or 8.192 Mb/s) the A6 input should be connected to pin STo6/A6.
ST-BUS Input 7/Addr.7 input
(5V-tolerant Input): The function of this pin is determined
by the switching configuration enabled. If non-multiplexed CPU bus is used along with
a higher input rate of 8.192 Mb/s, this pin provides A7 address input function.
For 2.048 and 4.096 Mb/s (8x4) applications or when the multiplexed CPU bus is
selected, this pin assumes STi7 function. See Control Register bits description and
Tables 1, 2, 6 & 7 for more details.
Note that for applications where both A7 and STi7 inputs are required simultaneously
(e.g., 2.048 to 8.192 Mb/s rate conversion) the A7 input should be connected to pin
STo7/A7.
STi6/A6
11
11
STi7/A7
2
MITEL [ MITEL NETWORKS CORPORATION ]
