MT89L86
Advance Information
t
CK
VHM
VLM
CLK
(4.096 or
8.192
MHz)
t
t
CH
CL
t
t
t
FH
FS
VHM
VLM
FR
(positive)
t
FW
DD
t
t
ZA
AZ
VHM
VLM
Ch. 0
Bit 7
Ch. 0
Bit 6
Ch. 0
Bit 5
Ch. 63 or 127
Bit 5
STo
STi
High Z
t
t
DS
DH
VHM
VLM
B0
B7
B6
B5
VHM
VLM
CLK
(4.096
MHz)
t
t
FH
FS
VHM
VLM
FR
(negative)
t
FW
t
DD
VHM
VLM
Ch. 63
Bit 0
Ch. 0
Bit 7
Ch. 0
Bit 6
Ch. 0
Bit 5
STo
STi
t
t
DH
DS
VHM
VLM
B0
B7
B6
B5
Figure 19 - Serial Interface Timing (CLKM bit=1, DMO bit=0) - 4.096 and 8.192 Mb/s
Note: For 8.192 Mb/s clock, only the positive polarity frame pulse is accepted by the 3.3V MT89L86.
VHM
ODE
VLM
VHM
VLM
STo0
to
STo9
*
*
t
t
OED
OED
Figure 20 - Output Driver Enable for Streams at 4.096 and 8.192 Mb/s
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