MT89L85
Advance Information
STi3
STi4
STi5
STi6
STi7
V
DD
F0i
C4i
A0
A1
A2
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
STo3
STo4
STo5
STo6
STo7
V
SS
D0
D1
D2
D3
D4
44 PIN PLCC
V
SS
DTA
STi0
STi1
STi2
NC
STi3
STi4
STi5
STi6
STi7
V
DD
RESET
F0i
C4i
A0
A1
A2
NC
A3
A4
A5
DS
R/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CSTo
ODE
STo0
STo1
STo2
NC
STo3
STo4
STo5
STo6
STo7
V
SS
V
DD
D0
D1
D2
D3
D4
NC
D5
D6
D7
CS
V
SS
NC
A3
A4
A5
DS
R/W
CS
D7
D6
D5
NC
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
NC
STi2
STi1
STi0
DTA
CSTo
ODE
STo0
STo1
STo2
NC
48 PIN SSOP
(JEDEC MO-118, 300mil Wide)
Figure 2 - Pin Connections
Pin Description
Pin #
44
PLCC
2
3-5
7-11
12
48
SSOP
2
3-5
7-11
12,36
13
Name
Description
DTA
Data Acknowledgment (Open Drain Output).
This active low output indicates that a
data bus transfer is complete. A pull-up resistor is required at this output.
STi0-
ST-BUS Input 0 to 7 (Inputs).
Serial data input streams. These streams have 32
STi7 channels at data rates of 2.048 Mbit/s.
V
DD
+3.3 Volt Power Supply.
RESET
Device Reset (5v-tolerant input).
This pin is only available for the 48-pin SSOP
package. This active low input puts the MT89L85 in its reset state. It clears the internal
counters anf registers. All ST-BUS outputs are set to the high impedance state. This
RESET pin must be held low for a minimum of 100nsec to reset the device.
F0i
Frame Pulse (Input).
This input accepts and automatically identifies frame
synchronization signals formatted according to different backplane specifications such
as ST-BUS and GCI.
Clock (Input).
4.096 MHz serial clock for shifting data in and out of the data streams.
13
14
14
15-17
19-21
22
15
16-18
20-22
23
C4i
A0-A5
Address 0 to 5 (Inputs).
These lines provide the address to MT89L85 internal
registers.
DS
Data Strobe (Input).
This is the input for the active high data strobe on the
microprocessor interface. This input operates with CS to enable the internal read and
write generation.
2
MITEL [ MITEL NETWORKS CORPORATION ]
