MT8986
The Control and Interface Mode Selection registers
together control all the major functions of the device.
The Interface Mode Select register should be set up
during system power-up to establish the desired
switching configuration as explained in the Serial
Interface and Switching Configurations sections.
The Control register is dynamically used by the CPU
to control switching operations in the MT8986. The
Control register selects the device's internal
memories and its subsections to specify the input
and output channels selected for switching
procedures.
The data in the Control register consists of Split
memory and Message mode bits, Memory select and
Stream Address bits. The memory select bits allow
the Connect Memory HIGH or LOW or the Data
Memory to be chosen, and the Stream Address bits
define
an
internal
memory
subsections
corresponding to input or output ST-BUS streams.
Bit 7 (Slip Memory) of the Control register allows split
memory operation whereby reads are from the Data
memory and writes are to the Connect Memory
LOW.
The Message Enable bit (bit 6) places every output
channel on every output stream in message mode;
i.e., the contents of the Connect Memory LOW
(CML) are output on the ST-BUS output streams
once every frame unless the ODE input pin is LOW.
If ME bit is HIGH, then the MT8986 behaves as if bits
2 (Message Channel) and 0 (Output Enable) of every
A7
X
X
X
X
0
0
•
•
0
0
0
•
•
0
1
•
•
1
A6
X
X
X
X
0
0
•
•
0
1
1
•
•
1
0
•
•
1
A5
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A4
0
0
0
0
0
0
•
•
1
0
0
•
•
1
0
•
•
1
A3
0
0
0
0
0
0
•
•
1
0
0
•
•
1
0
•
•
1
A2
0
0
0
0
0
0
•
•
1
0
0
•
•
1
0
•
•
1
A1
0
0
1
1
0
0
•
•
1
0
0
•
•
1
0
•
•
1
Connect Memory HIGH (CMH) locations were set to
HIGH, regardless of the actual value. If ME bit is
LOW, then bit 2 and 0 of each Connect Memory
HIGH location function normally. In this case, if bit 2
of the CMH is HIGH, the associated ST-BUS output
channel is in Message mode. If bit 2 of the CMH is
LOW, then the contents of the SAB and CAB bits of
the CMH and CML define the source information
(stream and channel) of the time-slot that is to be
switched to an output.
If the ODE input pin is LOW, then all serial outputs
are high-impedance. If ODE is HIGH, then bit 0
(Output Enable) of the CMH location enables (if
HIGH) or disables (if LOW) the output drivers for the
corresponding individual ST-BUS output stream and
channel.
The contents of bit 1 (CSTo) of each Connection
Memory High location is output on CSTo pin once
every frame. The CSTo pin is a 2048 Mbit/s output
which carries 256 bits. If CSTo bit is set HIGH, the
corresponding bit on CSTo output is transmitted
HIGH. If CSTo bit is LOW, the corresponding bit on
the CSTo output is transmitted LOW. The contents of
the 256 CSTo bits of the CMH are transmitted
sequentially on to the CSTo output pin and are
synchronous to the 2.048 Mb/s ST-BUS streams. To
allow for delay in any external control circuitry the
contents of the CSTo bit is output one channel before
the corresponding channel on the ST-BUS streams.
For example, the contents of CSTo bit in position 0
(ST0, CH0) of the CMH, is transmitted
synchronously with ST-BUS channel 31, bit 7. The
contents of CSTo bit in position 32 (ST1, CH0) of the
A0
0
1
0
1
0
1
•
•
1
0
1
•
•
1
0
•
•
1
Location
Control Register
Interface Mode Select Register
Stream Pair Select Register
Frame Input Offset Register
Channel 0*
Channel 1*
•
•
Channel 31*
Channel 32**
Channel 33**
•
•
Channel 63**
Channel 64***
•
•
Channel 127***
Table 5. Address Memory Map
*:
channels 0 to 31 are used in 2.048 Mb/s (8 x 8, 16 x 8 and 10 x 10)
**: channels 0 to 63 are used in 4.096 Mb/s (Nibble Switching, 4 x 4, 8 x 4 or Different I/O rates)
***: channels 0 to 127 are used in 8.192 Mb/s (2 x 2 or Different I/O rates)
2-73
MITEL [ MITEL NETWORKS CORPORATION ]
