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MT8985 参数 Datasheet PDF下载

MT8985图片预览
型号: MT8985
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS ST- BUS⑩系列增强型数字式开关 [CMOS ST-BUS⑩ FAMILY Enhanced Digital Switch]
分类和应用: 开关
文件页数/大小: 18 页 / 326 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT8985  
Absolute Maximum Ratings*  
Parameter  
Symbol  
Min  
Max  
Units  
1
2
3
4
5
6
VDD - VSS  
-0.3  
7
VDD+0.3  
VDD+0.3  
40  
V
V
Voltage on Digital Inputs  
Voltage on Digital Outputs  
Current at Digital Outputs  
Storage Temperature  
VI  
VO  
IO  
VSS-0.3  
VSS-0.3  
V
mA  
°C  
W
TS  
-65  
+150  
2
Package Power Dissipation  
PD  
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.  
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.  
Characteristics  
Sym  
Min  
Typ  
Max  
Units  
Test Conditions  
1
2
3
Operating Temperature  
Positive Supply  
TOP  
VDD  
VI  
-40  
4.75  
0
25  
+85  
5.25  
VDD  
°C  
V
5.0  
Input Voltage  
V
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.  
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.  
Characteristics  
Supply Current  
Sym  
Min  
Typ  
Max Units  
Test Conditions  
1
2
3
4
IDD  
VIH  
VIL  
IIL  
10  
15  
mA  
V
Outputs unloaded  
I
Input High Voltage  
Input Low Voltage  
2.0  
N
P
U
T
S
0.8  
V
Input Leakage (input pins)  
Input Leakage (I/O pins)  
5
µA  
VI between VSS and VDD  
34  
8
100  
5
6
Input Pin Capacitance  
Output High Voltage  
Output High Current  
Output Low Voltage  
CI  
VOH  
IOH  
VOL  
IOL  
pF  
V
2.4  
10  
IOH = 10 mA  
O
U
T
P
U
T
7
15  
10  
8
mA  
V
Sourcing. VOH=2.4V  
IOL = 5 mA  
8
0.4  
5
9
Output Low Current  
High Impedance Leakage  
Output Pin Capacitance  
5
mA  
µA  
pF  
Sinking. VOL = 0.4V  
VO between VSS and VDD  
10  
IOZ  
S
11  
CO  
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.  
S1 is open circuit except  
when testing output levels  
or high impedance states.  
VDD  
Test Point  
S2 is switched to V or  
SS  
levels or high impedance  
states.  
DD  
R
L
Output  
Pin  
V
when testing output  
S1  
S2  
C
L
V
V
SS  
SS  
Figure 12 - Output Test Load  
2-57  
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