ISO-CMOS MT8982
AC Electrical Characteristics† - TDM Bus (See Figures 13 and 14a, 14b). Voltages are with
respect to ground (V ) unless otherwise stated.
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
4 meg mode
1
2
Frame Pulse Input Setup Time
Frame Pulse Input Hold Time
tfs
tfh
10
5
ns
ns
5
cycles
3
4
5
Serial Output Delay;
Active to Active
tsdaa
tsdaz
tsdza
100
ns
ns
ns
CL=50pF
Serial Output Delay;
Active to High Z
200
150
CL=50pF
RL=1kΩ*
Serial Output Delay;
High Z to Active
CL=150pF
6
7
8
9
Serial Input Setup Time
Serial Input Hold Time
tss
tsh
20
10
ns
ns
ns
ns
ns
ns
ns
ns
Frame Pulse Output Delay
ODE Low to Serial Out High Z
tfd
70
125
50
tsaz
tsza
tc4l
tc4h
tc4
CL=50pF, RL=1kΩ*
CL=50pF, RL=1kΩ
tc4 = 244 ns
10 ODE High to Serial Out Active
11 C4 Clock Pulse Width Low
12 C4 Clock Pulse Width High
13 C4 Clock Period
25
35
100
100
244
209
219
tc4 = 244 ns
150
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High impedance is measured by pulling to the appropriate rail with R , with timing corrected to cancel time taken to discharge C .
L
L
t
t
fd
fd
t
c4
F0o (ST-BUS)
C4i
t
t
c4l
c4h
F0o (GCI)
t
t
fd
fd
Figure 14a - TDM Bus Timing - F0o/Clock Timing
ODE
STo0-1
t
t
sza
saz
Figure 14b - ODE Timing
2-43
MITEL [ MITEL NETWORKS CORPORATION ]
