ISO-CMOS MT8981D
AC Electrical Characteristics† - Processor Bus (Figures 11 and 17)
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
Chip Select Setup Time
Read/Write Setup Time
Address Setup Time
Acknowledgement Delay Fast
Slow
tCSS
tRWS
tADS
tAKD
tAKD
tFWS
tSWD
tRDS
tDHT
tDHT
tRDZ
tCSH
tRWH
tADH
tAKH
20
25
25
0
5
ns
ns
5
ns
40
100
7.2
ns
CL=150 pF
➀
2.7
20
cycles C4i cycles
ns
5
6
7
8
Fast Write Data Setup Time
Slow Write Data Delay
Read Data Setup Time
➀
➀
2.0
1.7
0.5
cycles C4i cycles
cycles C4i cycles , CL= 150 pF
Data Hold Time
Read
Write
20
20
ns
ns
ns
ns
ns
ns
ns
RL=1 KΩ , CL=150 pF
RL=1 KΩ , CL=150 pF
10
50
9
Read Data To High Impedance
90
10 Chip Select Hold Time
11 Read/Write Hold Time
12 Address Hold Time
0
0
0
13 Acknowledgement Hold Time
10
60
80
RL=1 KΩ , CL=150 pF
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with R , with timing corrected to cancel time taken to discharge C .
L
L
➀ Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period.
2.0V
DS
0.8V
2.0V
CS
0.8V
t
t
t
t
CSS
CSH
RWH
ADH
2.0V
0.8V
R/W
t
t
RWS
ADS
2.0V
0.8V
A5
to
A0
t
AKD
t
AKH
2.4V
0.4V
*
*
DTA
t
RDS
t
DHT
2.4V (Read) 2.0V (Write)
0.8V (Read 0.8V (Write)
D7
to
D0
*
*
t
FWS
t
t
RDZ
SWD
Figure 17 - Processor Bus
2-29
MITEL [ MITEL NETWORKS CORPORATION ]
