MT8981D
ISO-CMOS
Line Interface Circuit
with Codec (e.g. 8964)
4
Speech
Switch
-
8981
STi0-3
Line 1
4
STo0-3
Controlling
Micro-
Processor
STo0-3
4
STi0-3
•
•
•
Repeated for Lines
2 to 127
•
•
•
Repeated for Lines
2 to 127
4
Control &
Signalling
-
8981
Line Interface Circuit
with Codec (e.g. 8964)
Line 128
Figure 8 - Example Architecture of a Simple Digital Switching System
Application Circuit with 6802 Processor
Fig. 10 shows an example of a complete circuit
which may be used to evaluate the chip.
For convenience, a 4 MHz crystal oscillator has been
used rather than a 4.096 MHz clock, as both are
within the limits of the chip’s specifications. The RC
delay used with the 393 counters ensures a
sufficient hold time for the FP signal, but the values
used may have to be changed if faster 393 counters
become available.
The chip is shown as memory mapped into the
MEK6802D3 system. Chip addresses 00-3F
correspond to processor addresses 2000-203F.
Delay through the address decoder requires the
VMA signal to be used twice to remove glitches. The
MEK6802D3 board uses a 10KΩ pullup on the MR
pin, which would have to be incorporated into the
circuit if the board was replaced by a processor.
8981
#1
IN 0/3
STi0/3 STo0/3
OUT 0/3
8981
#2
STi0/3 STo0/3
OUT 4/7
8981
#3
IN 4/7
STi0/3 STo0/3
8981
#4
STi0/3 STo0/3
Figure 9 - Four 8981s Arranged in a Non-Blocking 8 x 8 Configuration
2-24
MITEL [ MITEL NETWORKS CORPORATION ]
