MT8980D
AC Electrical Characteristics† - Clock Timing (Figures 12 and 13)
‡
Characteristics
Clock Period*
Sym
Min
Typ
Max Units
Test Conditions
1
2
3
4
5
6
7
tCLK
tCH
220
95
244
122
122
20
300
150
150
ns
ns
ns
ns
ns
µs
ns
Clock Width High
I
Clock Width Low
tCL
110
N
P
U
T
S
Clock Transition Time
Frame Pulse SetupTime
Frame Pulse Hold Time
Frame Pulse Width
tCTT
tFPS
tFPH
tFPW
20
200
50
0.020
244
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state.
NB: Frame Pulse is repeated every 512 cycles of C4i.
C4i
F0i
BIT
CELLS
Channel 31
Bit o
Channel 0
Bit 7
Figure 12 - Frame Alignment
t
CLK
t
t
t
CH
CL
CTT
2.0V
C4i
F0i
0.8V
t
t
CHL
CTT
t
t
FPS
FPH
t
t
FPH
FPS
2.0V
0.8V
t
FPW
Figure 13 - Clock Timing
2-13
MITEL [ MITEL NETWORKS CORPORATION ]
