MT8980D
AC Electrical Characteristics
†
- Processor Bus (Figures 11 and 17)
Characteristics
1
2
3
4
Chip Select Setup Time
Read/Write Setup Time
Address Setup Time
Acknowledgement Delay Fast
Slow
5
6
7
8
Fast Write Data Setup Time
Slow Write Data Delay
Read Data Setup Time
Data Hold Time
Read
Write
9
10
11
12
13
Read Data To High Impedance
Chip Select Hold Time
Read/Write Hold Time
Address Hold Time
Acknowledgement Hold Time
Sym
t
CSS
t
RWS
t
ADS
t
AKD
t
AKD
t
FWS
t
SWD
t
RDS
t
DHT
t
DHT
t
RDZ
t
CSH
t
RWH
t
ADH
t
AKH
0
0
0
10
60
80
20
20
10
50
90
2.7
20
2.0
1.7
0.5
Min
20
25
25
Typ
‡
0
5
5
40
100
7.2
Max
Units
ns
ns
ns
ns
cycles
ns
cycles
cycles
ns
ns
ns
ns
ns
ns
ns
R
L
=1 KΩ
∗
, C
L
=150 pF
R
L
=1 KΩ
∗
, C
L
=150 pF
C4i cycles
C4i cycles
, C
L
= 150 pF
R
L
=1 KΩ
∗
, C
L
=150 pF
C
L
=150 pF
C4i cycles
Test Conditions
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge C
L
.
Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period.
2.0V
DS
0.8V
2.0V
CS
0.8V
t
CSS
2.0V
R/W
0.8V
t
RWS
A5
to
A0
2.0V
0.8V
t
ADS
t
AKD
t
AKH
2.4V
DTA
0.4V
t
RDS
D7
to
D0
2.4V (Read) 2.0V (Write)
0.8V (Read 0.8V (Write)
t
DHT
t
ADH
t
RWH
t
CSH
*
*
*
t
SWD
t
FWS
t
RDZ
*
Figure 17 - Processor Bus
2-15
MITEL [ MITEL NETWORKS CORPORATION ]
