ISO-CMOS
which contain the non-frame alignment pattern
contain within the bit 1 position, a 6 bit CRC
multiframe alignment signal and two spare bits (in
frames 13 and 15), which are used for CRC error
performance reporting (refer to Figure 6). During the
CRC encoding procedure the CRC bit positions are
initially set at zero. The remainder of the calculation
is stored and inserted into the respective CRC bits of
the next SMF. The decoding process repeats the
multiplication division process and compares the
remainder with the CRC bits received in the next
SMF.
The two spare bits (denoted Si1 and Si2 in Figure 6)
in the CRC-4 multiframe are used to monitor far-end
error performance.
The results of the CRC-4
comparisons for the previously received SMFII and
SMFI are encoded and transmitted back to the far
end in the Si bits (refer to Table 1).
Si1 bit
(frame
13)
1
1
0
0
Si2 bit
(frame
15)
1
0
1
0
MT8979
Meaning
CRC results for both SMFI, II are
error free.
CRC result for SMFII is in error.
CRC result for SMFI is error free.
CRC result for SMFII is error free.
CRC result for SMFI is in error.
CRC results for both SMFI, II are
in error.
Table 1. Coding of Spare Bits Si1 and Si2
Data Input (DSTi)
The MT8979 receives information channels on the
DSTi pin. Of the 32 available channels on this
serial input, 30 are defined as information channels.
They are channels 1-15 and 17-31. These 30
timeslots are the 30 telephone channels of the CEPT
format numbered 1-15 and 16-30. Timeslot 0 and 16
are unused to allow the synchronization and
signalling information to be inserted, from the Control
Streams (CSTi0 and CSTi1). The relationship
between the input and output ST-BUS stream and
the CEPT line is illustrated in Figures 8 to 12. In
common channel signalling mode timeslot 16
becomes an active channel. In this mode channel 16
on DSTi is transmitted on timeslot 16 of the CEPT
link unaltered. This mode is activated by bit 5 of
channel 31 of CSTi0.
ST-BUS Interface
The ST-BUS is a synchronous time division
multiplexed serial bus with data streams operating at
2048 kbit/s and configured as 32, 64 kbit/s channels
(refer Figure 7). Synchronization of the data transfer
is provided from a frame pulse, which identifies the
frame boundaries and repeats at an 8 kHz rate.
Figure 17 shows how the frame pulse (F0i) defines
the ST-BUS frame boundaries. All data is clocked
into the device on the falling edge of the 2048 kbit/s
clock (C2i), while data is clocked out on the rising
edge of the 2048 kbit/s clock at the start of the bit
cell.
Bit Number
1
Timeslot 0 containing the
frame alignment signal
Timeslot 0 containing the
non-frame alignment signal
Reserved for
International
use
(1)
Reserved for
International
use
(2)
2
0
3
0
4
1
5
1
6
0
7
1
8
1
1
Alarm indication to the
remote PCM multiplex
equipment
See
Note
#3
See
Note
#3
See
Note
#3
See
Note
#3
See
Note
#3
Figure 4 - Allocation of Bits in Timeslot 0 of the CEPT Link
Note 1 : With CRC active, this bit is ignored.
Note 2 : With SiMUX active, this bit transmits SMF CRC results in frames 13 and 15
Note 3 : Reserved for National use
.
Timeslot 16 of frame 0
Timeslot 16 of frame 1
ABCD bits for
telephone
channel 1
(timeslot 1)
ABCD bits for
telephone
channel 16
(timeslot 17)
Timeslot 16 of frame 15
•••
0000
XYXX
ABCD bits for
telephone
channel 15
(timeslot 15)
ABCD bits for
telephone
channel 30
(timeslot 31)
Figure 5 - Allocation of Bits in Timeslot 16 of the CEPT Link
4-165
MITEL [ MITEL NETWORKS CORPORATION ]
