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MT8979AE 参数 Datasheet PDF下载

MT8979AE图片预览
型号: MT8979AE
PDF下载: 下载PDF文件 查看货源
内容描述: ISO- CMOS ST- BUS⑩家庭CEPT PCM 30 / CRC - 4成帧器和接口 [ISO-CMOS ST-BUS⑩ FAMILY CEPT PCM 30/CRC-4 Framer & Interface]
分类和应用: PC
文件页数/大小: 26 页 / 343 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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ISO-CMOS
MT8979
BIT
7
NAME
DATA
DESCRIPTION
Data Channel:
If ‘1‘, then the controlled timeslot on the CEPT 2048 kbit/s link is
treated as a data channel; i.e., no ADI encoding or decoding is performed on
transmission or reception, and digital attenuation is disabled.
If ‘0‘, then the state of the ADI pin determines whether or not ADI encoding and
decoding is performed.
Per-Channel Loopback:
If ‘1‘, then the controlled timeslot on the transmitted
CEPT 2048 kbit/s link is looped internally to replace the data on the corresponding
received timeslot. If ‘0‘, then this function is disabled.
This function only operates if frame synchronization is received from the CEPT link.
If more than one channel is looped per frame only the first one will be active.
Receive Attenuation Pad:
Per timeslot receive attenuation control bits.
RXPAD4
0
0
0
0
1
1
1
1
RXPAD2
0
0
1
1
0
0
1
1
RXPAD1
0
1
0
1
0
1
0
1
Gain (dB)
0
-1
-2
-3
-4
-5
-6
1
6
LOOP
5,4,3
RXPAD4,2,1
2,1,0
TXPAD4,2,1
Transmit Attenuation Pad:
Per timeslot transmit attenuation control bits.
TXPAD4
0
0
0
0
1
1
1
1
TXPAD2
0
0
1
1
0
0
1
1
TXPAD1
0
1
0
1
0
1
0
1
Gain (dB)
0
-1
-2
-3
-4
-5
-6
1
Table 2. Per Channel Control Word: Data Format for CSTi0 Channels 0-14, and 16-30
BIT
7
6
NAME
(N/A)
LOOP16
Keep at ‘1‘ for normal operation.
DESCRIPTION
Channel 16 Loopback:
If ‘1‘, then timeslot 16 on the transmitted CEPT 2048 kbit/s link
is looped internally to replace the data received on timeslot 16.
If ‘0,‘ then this function is disabled.
This function only operates if frame synchronization is received from the CEPT link and
only a single timeslot can be looped within the frame.
Keep at ‘1‘ for normal operation.
5,4
3,2,
1
&0
(N/A)
NDBD, NDBC, Signalling Bit Debounce:
If ‘1‘, then no debouncing is applied to the received A, B, C or
NDBB
D signalling bits. If ‘0‘, then the received A, B, C or D signalling bits are debounced for
& NDBA
between 6 and 8 ms.
Table 3. Master Control 1 (MCW1): Data Format for CSTi0 Channel 15
4-171