MT8976
ISO-CMOS
TxA
TxB
DSTo
NC
VSS
VDD
IC
NC
F0i
NC
E1.5i
28 PIN CERDIP/PDIP
Figure 2 - Pin Connections
VSS
CSTi0
E8Ko
NC
VSS
XCtl
DSTi
RxFDLClk
CSTo
NC
XSt
44 PIN PLCC
TxA
TxB
DSTo
NC
RxA
RxB
RxD
CSTi1
TxFDL
TxFDLClk
NC
CSTi0
E8Ko
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
IC
F0i
E1.5i
C1.5i
RxSF
TxSF
C2i
RxFDL
DSTi
RxFDLClk
CSTo
XSt
XCtl
NC
NC
RxA
RxB
RxD
NC
CSTi1
TxFDL
NC
TxFDLClk
NC
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
C1.5i
RxSF
TxSF
NC
NC
C2i
NC
NC
NC
NC
RxFDL
Pin Description
Pin #
DIP
PLCC
.
Name
TxA
TxB
DSTo
NC
RxA
Description
Transmit A Output.
Unipolar output that can be used in conjunction with TxB and
external line driver circuitry to generate the bipolar DS1 signal.
Transmit B Output.
Unipolar output that can be used in conjunction with TxA and
external line driver circuitry to generate the bipolar DS1 signal.
Data ST-BUS Output.
A 2048 kbit/s serial output stream which contains the 24
PCM or data channels received from the DS1 line.
No Connection.
Receive A Complementary Input.
Accepts a unipolar split phase signal decoded
externally from the received DS1 bipolar signal. This input, in conjunction with RxB,
detects bipolar violations in the received signal.
Receive B Complementary Input.
Accepts a unipolar split phase signal decoded
externally from the received DS1 bipolar signal. This input, in conjunction with RxA,
detects bipolar violations in the received signal.
Receive Data Input.
Unipolar RZ data signal decoded from the received DS1
signal. Generally the signals input at RxA and RxB are combined externally with a
NAND gate and the resulting composite signal is input at this pin.
Control ST-BUS Input #1.
A 2048 kbit/s serial control stream which carries 24 per-
channel control words.
Transmit Facility Data Link (Input).
A 4 kHz serial input stream that is multiplexed
into the FDL position in the ESF mode, or the F
s
pattern when in SLC-96 mode. It is
clocked in on the rising edge of TxFDLClk.
Transmit Facility Data Link Clock (Output).
A 4 kHz clock used to clock in the FDL
data.
No connection.
1
2
3
4
5
2
3
5
4
9
6
10
RxB
7
11
RxD
8
9
13
14
CSTi1
TxFDL
10
11
16
TxFDLClk
NC
4-30
MITEL [ MITEL NETWORKS CORPORATION ]
