MT8976 ISO-CMOS
1
2
3
4
5
6
7
TxA
TxB
DSTo
NC
RxA
RxB
RxD
VDD
IC
F0i
E1.5i
C1.5i
RxSF
TxSF
C2i
RxFDL
DSTi
40
44 43 42 41
28
27
26
25
24
23
22
21
20
19
18
17
16
15
6
5
4
3
2
1
C1.5i
RxSF
7
NC
NC
RxA
39
8
38
37
36
35
34
33
32
31
30
29
9
TxSF
10
11
12
13
14
15
16
NC
RxB
RxD
NC
NC
C2i
CSTi1
NC
8
9
CSTi1
TxFDL
TxFDLClk
NC
NC
TxFDL
NC
NC
10
11
12
13
14
TxFDLClk
NC
NC
RxFDLClk
CSTo
XSt
RxFDL
17
18 19 20 21 22 23 24 25 26 27 28
CSTi0
E8Ko
VSS
XCtl
28 PIN CERDIP/PDIP
44 PIN PLCC
Figure 2 - Pin Connections
.
Pin Description
Pin #
Name
TxA
Description
DIP
PLCC
1
2
Transmit A Output. Unipolar output that can be used in conjunction with TxB and
external line driver circuitry to generate the bipolar DS1 signal.
2
3
3
5
TxB
Transmit B Output. Unipolar output that can be used in conjunction with TxA and
external line driver circuitry to generate the bipolar DS1 signal.
DSTo
Data ST-BUS Output. A 2048 kbit/s serial output stream which contains the 24
PCM or data channels received from the DS1 line.
4
5
4
9
NC
No Connection.
RxA
Receive A Complementary Input. Accepts a unipolar split phase signal decoded
externally from the received DS1 bipolar signal. This input, in conjunction with RxB,
detects bipolar violations in the received signal.
6
7
10
11
RxB
RxD
Receive B Complementary Input. Accepts a unipolar split phase signal decoded
externally from the received DS1 bipolar signal. This input, in conjunction with RxA,
detects bipolar violations in the received signal.
Receive Data Input. Unipolar RZ data signal decoded from the received DS1
signal. Generally the signals input at RxA and RxB are combined externally with a
NAND gate and the resulting composite signal is input at this pin.
8
9
13
14
CSTi1
Control ST-BUS Input #1. A 2048 kbit/s serial control stream which carries 24 per-
channel control words.
TxFDL
Transmit Facility Data Link (Input). A 4 kHz serial input stream that is multiplexed
into the FDL position in the ESF mode, or the Fs pattern when in SLC-96 mode. It is
clocked in on the rising edge of TxFDLClk.
10
11
16
TxFDLClk Transmit Facility Data Link Clock (Output). A 4 kHz clock used to clock in the FDL
data.
NC
No connection.
4-30
MITEL [ MITEL NETWORKS CORPORATION ]
