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MT8972BP 参数 Datasheet PDF下载

MT8972BP图片预览
型号: MT8972BP
PDF下载: 下载PDF文件 查看货源
内容描述: ISO2 -CMOS ST- BUS⑩家庭数字用户接口电路数字网络接口电路 [ISO2-CMOS ST-BUS⑩ FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit]
分类和应用: 网络接口电信集成电路综合业务数字网
文件页数/大小: 20 页 / 393 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT8971B/72B  
C-Channel  
(Bit 0-7)  
Internal Control Internal Diagnostic  
Description  
Register  
Register  
XXX01111  
00000000  
01000000  
Default Mode-1 : Bit rate is 80 kbit/s. ATTACK,  
PSEN, DINB, DRR and all diagnostics are disabled.  
TxHK=0.  
XXX11111  
00010000  
01000000  
Default Mode-2 Bit rate is 160 kbit/s. ATTACK,  
PSEN, DINB, DRR and all diagnostics are disabled.  
TxHK=0.  
Table 4a. Default Mode Selection  
Notes:  
Default Mode 1 can also be selected by tying CDSTi/CDi pin low when DNIC is operating in dual mode.  
Default Mode 2 can also be selected by tying CDSTi/CDi pin high when DNIC is operating in dual mode.  
bit 0  
bit 1  
bit 2  
bit 3  
bit 4  
bit 5  
bit 6  
bit 7  
Reg Sel-1  
Reg Sel-2  
Loopback  
FUN  
PSWAP  
DLO  
Not Used  
Default Mode Selection  
(Refer to Table 4a)  
Bit  
Name  
Description  
0
1
Reg Sel-1  
Reg Sel-2  
Loopback  
Register Select-1. Must be set to ’0’ to select the Diagnostic Register.  
Register Select-2. Must be set to ’1’ to select the Diagnostic Register.  
Bit 2 Bit 3  
2,3  
0
0
1
1
0
1
0
1
All loopback testing functions disabled. Normal operation.  
DSTi internally looped back into DSTo for system diagnostics.  
L
OUT is internally looped back into LIN for system diagnostics.  
DSTo is internally looped back into DSTi for end-to-end testing.  
4
5
FUN  
Force Unsync. When set to ’1’, the DNIC is forced out-of-sync to test the SYNC  
recovery circuitry. When set to ’0’, the operation continues in synchronization.  
PSWAP  
Polynomial Swap. When set to ’1’, the scrambling and descrambling polynomials  
are interchanged (use for MAS mode only). When set to ’0’, the polynomials retain  
their normal designations.  
6
7
DLO  
Disable Line Out. When set to ’1’, the signal on LOUT is set set to VBias. When set to  
’0’, LOUT pin functions normally.  
Not Used  
Must be set to ’0’ for normal operation.  
Table 5. Diagnostic Register  
Notes:  
When bits 4-7 of the Diagnostic Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,  
depending upon the status of bit-3.  
Do not use LOUT to LIN loopback in DN/SLV mode.  
Do not use DSTo to DSTi loopback in MOD/MAS mode.  
and CLD with TCK defining the bits and CLD the  
channel boundaries of the data stream as shown in  
Figure 8.  
from the line. The line code used in the DNIC is  
Biphase and is shown in Figure 10. The scrambled  
NRZ data is differentially encoded meaning the  
previous differential encoded output is XOR’d with  
the current data bit which produces the current  
output. This is then biphase encoded where  
transitions occur midway through the bit cell with a  
negative going transition indicating a logic "0" and a  
positive going transition indicating a logic "1".  
Line Port (LIN, LOUT  
)
The line interface is made up of LOUT and LIN with  
LOUT driving the transmit signal onto the line and LIN  
receiving the composite transmit and receive signal  
9-117