ISO-CMOS
Pin Description (continued)
Pin No.
11
12
13
14
15-22
23
Name
CS
E
R/W
V
SS
D0-D7
REOP
Description
MT8952B
Chip Select Input
- This is an active LOW input enabling the Read or Write operation to
various registers in the Protocol Controller.
Enable Clock Input
- This input activates the Address Bus and R/W input and enables
data transfers on the Data Bus.
Read/Write Control -
This input controls the direction of data flow on the data bus. When
HIGH, the I/O buffer acts as an output driver and as an input buffer when LOW.
Ground (0 Volt).
Bidirectional Data Bus -
These Data Bus I/O ports allow the data transfer between the
HDLC Protocol Controller and the microprocessor.
Receive End Of Packet (Output) -
This is a HIGH going pulse that occurs for one bit
duration when a closing flag is detected on the incoming packets, or the incoming packet is
aborted, or when an invalid packet of 24 or more bits is received.
Transmit End Of Packet (Output) -
This is a HIGH going pulse that occurs for one bit
duration when a packet is transmitted correctly or aborted.
Clock Input (Bit rate clock or 2 x bit rate clock in ST-BUS format while in the Internal
Timing Mode and bit rate Clock in the External Timing Mode)
- This is the clock input
used for shifting in/out the formatted packets. It can be at bit rate (C2i) or twice the bit rate
(C4i) in ST-BUS format while the Protocol Controller is in the Internal Timing Mode.
Whether the clock should be C2i (typically 2.048 MHz) or C4i (typically 4.096 MHz) is
decided by the BRCK bit in the Timing Control Register. If the Protocol Controller is in the
External Timing Mode, it is at the bit rate.
Frame Pulse Input -
This is the frame pulse input in ST-BUS format to establish the
beginning of the frame in the Internal Timing Mode. This is also the signal clocking the
watchdog timer.
RESET Input -
This is an active LOW Schmitt Trigger input, resetting all the registers
including the transmit and receive FIFOs and the watchdog timer.
Supply (5 Volts).
24
25
TEOP
CKi
26
F0i
27
28
RST
V
DD
Address Bits
A3
0
0
0
0
0
0
0
0
1
1
A2
0
0
0
0
1
1
1
1
0
0
A1
0
0
1
1
0
0
1
1
0
0
A0
0
1
0
1
0
1
0
1
0
1
Read
FIFO Status
Receive Data
Control
Receive Address
C-Channel Control (Transmit)
Timing Control
Interrupt Flag
Interrupt Enable
General Status
Registers
Write
-
Transmit Data
Control
Receive Address
C-Channel Control (Transmit)
Timing Control
Watchdog Timer
Interrupt Enable
-
-
C-Channel Status (Receive)
Table 1. Register Addresses
3-63
MITEL [ MITEL NETWORKS CORPORATION ]
