MT8952B
ISO-CMOS
enables the associated interrupt source. However,
the masked bits in the IFR are still valid but they do
not cause the IRQ output to go LOW. The description
of the bits enabling the various interrupts is identical
to those of the Interrupt Flag Register.
General Status Register (Read):
This register (Figure 12) contains the general status
information on the Protocol Controller.
D7
D6
D5
GA
EOPD - End of Packet Detect:
A HIGH on this bit
confirms the reception of an ‘end of packet’ flag, an
abort sequence or an invalid packet of 24 or more
bits on the incoming data stream (CDSTi).
Tx DONE - Transmitter Done:
This bit, when HIGH,
indicates that the packet transmission is complete
and the Transmit FIFO is empty. The falling edge of
TEOP output causes this interrupt status bit to be set
HIGH if the FIFO is empty.
FA - Frame Abort:
This bit is set HIGH to indicate
that a frame abort has been detected on the
incoming data stream.
Tx 4/19 FULL - Transmit FIFO 4/19 full:
This bit if
set HIGH, indicates that the transmit FIFO has only 4
bytes remaining in it and another 15 bytes could be
loaded. This bit has significance only when the
transmit FIFO is being depleted and not when it is
getting loaded.
Tx URUN - Transmit FIFO underrun:
This bit when
HIGH, identifies that the transmit FIFO is empty
without the Protocol Controller being given the ‘end
of packet’ indication. This indicates that the transmit
FIFO has underrun and the Protocol Controller will
transmit an abort sequence automatically. Tx DONE
will be set 8 bit times after Tx URUN is set.
Rx15/19 FULL - Receive FIFO 15/19 full:
This bit
when HIGH, confirms that the receive FIFO has 15
bytes in it and it can receive four more bytes.
Rx OFLW - Receive FIFO overflow:
This bit when
set HIGH, indicates that the receive FIFO is full and
a ‘write’ occurred indicating an overflow. The byte
causing this and all the subsequent bytes written
while the FIFO is in this state are lost. The receiver
begins to search for a new start flag.
Watchdog Timer Register (Write):
The Watchdog Timer Register operates in
conjunction with the Watchdog Timer and the WD
output. Writing the code of XXX0 1010 in the register
resets the WD timer. If the register is not re-written
within 2
10
cycles of F0i after resetting the timer, the
WD output goes LOW. This register serves the sole
purpose of resetting the timer and hence relevant
only if it is written with the above data.
Interrupt Enable Register (Read/Write):
This register enables/disables the interrupts as
specified in the Interrupt Flag Register (IFR). Setting
HIGH the appropriate bits in this register (IER)
3-70
D4
ABRT
D3
IRQ
D2
IDLE
D1
LOW
D0
HIGH
Rx
Tx
OFLW URUN
Figure 12 - General Status Register
Rx OFLW - Receive FIFO overflow:
This bit, if set
HIGH, indicates that the receive FIFO has
overflowed. The byte causing this and all the
subsequent bytes written while the FIFO is in this
state are lost. Note that this bit is the same as the Rx
OFLW bit in Interrupt Flag Register (IFR) and can
only be cleared by reading the IFR.
Tx URUN - Transmit FIFO Underrun:
When HIGH,
this bit indicates that the transmit FIFO has
underrun. Under this condition the packet being
transmitted is aborted. This bit is the same as the Tx
URUN bit in the Interrupt Flag Register (IFR) and can
only be cleared when the IFR is read.
GA - Go Ahead:
This bit is set HIGH if a ‘go ahead’
is received on the incoming data stream and is
cleared when the Interrupt Flag Register is read.
This bit is the same as the GA bit in the IFR.
ABRT - Abort:
The reception of contiguous seven
ONEs on incoming data, sets this bit HIGH and
reading the General Status Register, clears it.
IRQ - Interrupt Request:
This bit refers to the status
of the interrupt request output from the Protocol
Controller. If HIGH, it indicates that the IRQ (pin 6)
output is LOW and vice versa.
IDLE - Idle Channel:
This bit, if set HIGH, identifies
that the receiver is detecting an idle channel at its
input (minimum 15 ONEs).
C-Channel Status Register (Read):
D7
CR7
D6
CR6
D5
CR5
D4
CR4
D3
CR3
D2
CR2
D1
CR1
D0
CR0
Figure 13. C-Channel Status Register
The C-Channel Register (Figure 13) continuously
stores the data received during the channel-1
MITEL [ MITEL NETWORKS CORPORATION ]
