MT8941B CMOS
MT8980/81
MT8941B
V
DD
MS0
MS1
MS2
MS3
ST-BUS
SWITCH
MH89790B
C4b
C2o
DSTi
C2i
F0i
C12i
DSTo
F0i
CSTi0
CSTi1
CSTo
OUTA
OUTB
RxT
EN
CV
E8Ko
C8Kb
C16i
Crystal Clock
F0b
(16.384 MHz)
EN
EN
C4o
CEPT
PRIMARY
MULTIPLEX
DIGITAL
LINK
TRANSMIT
RECEIVE
C2o
Y
o
V
SS
RST
RxR
Mode of Operation for the MT8941B
DPLL #1 - NOT USED
DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)
V
DD
R
C
Figure 12 - Synchronization at the Slave End of the CEPT Digital Transmission Link
Figures 11 and 12 show how the MT8941B can be
used to synchronize the ST-BUS to the CEPT
transmission link at the master and slave ends.
Figure 13 shows two such applications using DPLL
#2. In one case, the MT8941B is in FREE-RUN
mode with an oscillator input of 16.384 MHz. In the
other case, it is in NORMAL mode with the C8Kb
input tied to V . For these applications, DPLL #2
DD
Generation of ST-BUS Timing Signals
does not make any corrections and therefore, the
output signals are free from jitter. DPLL #1 is
completely free.
The MT8941B can source the properly formatted ST-
BUS timing and control signals with no external
inputs except the crystal clock. This can be used as
the standard timing source for ST-BUS systems or
any other system with similar clock requirements.
DPLL #1 - NOT USED
DPLL #2 - FREE-RUN MODE
(MS0=1; MS1=0;MS2=1;
MS3=1)
MT8941B
MT8941B
V
V
DD
MS0
MS1
MS2
MS3
DD
MS0
MS1
MS2
MS3
C4o
C4b
C4o
C4b
F0i
C12i
F0i
C12i
ST-BUS
ST-BUS
EN
EN
CV
CV
C8Kb
C16i
C8Kb
C16i
C2o
C2o
TIMING
TIMING
Crystal Clock
(16.384 MHz)
Crystal Clock
(16.384 MHz)
EN
EN
C4o
C4o
C2o
F0b
C2o
F0b
SIGNALS
SIGNALS
EN
EN
C2o
C2o
Ai
Bi
Ai
Bi
V
V
SS
DPLL #1 - NOT USED
DPLL #2 - NORMAL MODE
(MS0=0; MS1=0;
RST
SS
RST
MS2=1; MS3=1)
V
V
DD
DD
R
R
C
C
Figure 13 - Generation of the ST-BUS Timing Signals
12
MITEL [ MITEL NETWORKS CORPORATION ]
