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MT8940-1 参数 Datasheet PDF下载

MT8940-1图片预览
型号: MT8940-1
PDF下载: 下载PDF文件 查看货源
内容描述: ISO- CMOS ST- BUS⑩系列T1 / CEPT数字中继锁相环 [ISO-CMOS ST-BUS⑩ FAMILY T1/CEPT Digital Trunk PLL]
分类和应用:
文件页数/大小: 19 页 / 135 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT8940
ISO-CMOS
ENVC
MS0
C12i
MS1
F0i
F0b
MS2
C16i
ENC4o
C8Kb
C4o
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
RST
CV
CVb
Yo
Bi
Ai
MS3
ENC2o
C2o
C2o
C4b
Figure 2 - Pin Connections
Pin Description
Pin #
1
Name
EN
CV
Description
Variable clock enable (TTL compatible input)
- This input (pulled internally to V
DD
) directly
controls the three states of CV (pin 22) under all modes of operation. When HIGH, enables
CV and when LOW, puts it in high impedance condition. It also controls the three states of
CVb signal (pin 21) if MS1 is LOW. When EN
CV
is HIGH, the pin CVb is an output and when
LOW, it is in high impedance state. However, if MS1 is HIGH, CVb is always an input.
Mode select ‘0’ input (TTL compatible) -
This input (pulled internally to V
SS
) in conjunction
with MS1 (pin 4) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and
2).
Clock 12.355 MHz input (TTL compatible) -
Master clock input at 12.355 MHz
±100ppm
for
DPLL #1.
Mode select-1 input (TTL compatible) -
This input (pulled internally to V
SS
) in conjunction
with MS0 (pin 2) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and
2)
Frame pulse input (TTL compatible) -
This is the frame pulse input (pulled internally to
V
DD
) at 8 kHz. The DPLL #1 locks to the falling edge of this input to generate T1 (1.544
MHz) clock.
Frame pulse Bidirectional (TTL compatible input and Totem-pole output) -
Depending
on the minor mode selected for the DPLL #2, it provides the 8 kHz frame pulse output or acts
as an input (pulled internally to V
DD
) to an external frame pulse.
Mode select-2 input (TTL compatible) -
This input (pulled internally to V
DD
) in conjunction
with MS3 (pin 17) selects the minor mode of operation for the DPLL #2. (Refer to Table 3.)
Clock 16.388 MHz input (TTL compatible) -
Master clock input at 16.388 MHz±32 ppm for
DPLL #2.
Enable 4.096 MHz clock (TTL compatible input)
- This active high input (pulled internally
to V
DD
) enables C4o (pin 11) output. When LOW, the output C4o is in high impedance
condition.
2
MS0
3
4
C12i
MS1
5
F0i
6
F0b
7
8
9
MS2
C16i
EN
C4o
3-28