MT8931C
NC
NC
F0b
C4b
HALF
NC
VDD
VBias
LTx
NC
LRx
F0od
DSTi
DSTo
NC
NC
NC
XTAL2/NC
XTAL1/NT
NC
R/W/WR
DS/RD
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
NC
AS/ALE
CS
IRQ/NDA
VSS
NC
AD0
AD1
AD2
NC
NC
44 PIN PLCC
NC
STAR/Rsto
Rsti
NC
AD7
AD6
NC
AD5
AD4
AD3
NC
HALF
C4b
F0b
F0od
DSTi
DSTo
XTAL2/NC
XTAL1/NT
R/W/WR
DS/RD
AS/ALE
CS
IRQ/NDA
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VBias
LTx
LRx
STAR/Rsto
Rsti
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
28 PIN PDIP
Figure 2 - Pin Connections
Pin Description
Pin #
DIP PLCC
1
2
Name
HALF
Description
HALF Input/Output:
this is an input in NT mode and an output in TE mode identifying
which half of the S-interface frame is currently being written/read over the ST-BUS
(HALF = 0 sampled on the falling edge of C4b within the frame pulse low window,
identifies the information to be transmitted/received in the first half of the S-Bus frame
while HALF=1 identifies the information to be transmitted/received into the second half
of the S-Bus frame). Tying this pin to V
SS
or V
DD
in NT mode will allow the device to free
run. This signal can also be accessed from the ST-BUS C-channel.
4.096 MHz Clock:
a 4.096 MHz ST-BUS Data Clock input in NT mode.
In TE mode an output 4.096 MHz clock phase-locked to the line data signal.
Frame Pulse:
an active low frame pulse input indicating the beginning of active ST-
BUS channel times in NT mode. Frame pulse output in TE mode.
Delayed Frame Pulse Output:
an active low delayed frame pulse output indicating
the end of active ST-BUS channels for this device. Can be used to daisy chain
to other ST-BUS devices to share an ST-BUS stream.
Data ST-BUS Input:
a 2048 kbit/s serial PCM/data ST-BUS input with D, C, B1, and B2
channels assigned to the first four timeslots. These channels contain data to be
transmitted on the line and chip control information.
Data ST-BUS Output:
a 2048 kbit/s serial PCM/data ST-BUS output with D, C, B1 and
B2 channels assigned to the first four timeslots, respectively. The remaining timeslots
are placed into high impedance. These channels contain data received from the line
and chip status information.
2
3
4
3
4
7
C4b
F0b
F0od
5
8
DSTi
6
9
DSTo
7
13
XTAL2/IC
Crystal 2/Internal Connection:
in TE mode, XTAL1 and XTAL2 are to be connected to
an external 4.096 MHz parallel resonant crystal for the on-chip oscillator.
If XTAL1 is connected directly to a 4.096 MHz clock, this pin must be left unconnected.
In NT mode, this pin must be left unconnected.
XTAL1/NT
Crystal 1/Network Termination Mode Select Input:
for TE mode mode selection, a
4.096 MHz crystal is to be connected between the XTAL1 and XTAL2 pins, or a 4.096
MHz clock can be connected directly to XTAL1. For NT mode selection, this pin must
be tied to VDD. A pull-up resistor is needed when driven by a TTL device.
8
14
9-72
MITEL [ MITEL NETWORKS CORPORATION ]
