欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT8930CP 参数 Datasheet PDF下载

MT8930CP图片预览
型号: MT8930CP
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS ST- BUS⑩家庭用户网络接口电路 [CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit]
分类和应用: 网络接口电信集成电路综合业务数字网PC
文件页数/大小: 42 页 / 324 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
 浏览型号MT8930CP的Datasheet PDF文件第11页浏览型号MT8930CP的Datasheet PDF文件第12页浏览型号MT8930CP的Datasheet PDF文件第13页浏览型号MT8930CP的Datasheet PDF文件第14页浏览型号MT8930CP的Datasheet PDF文件第16页浏览型号MT8930CP的Datasheet PDF文件第17页浏览型号MT8930CP的Datasheet PDF文件第18页浏览型号MT8930CP的Datasheet PDF文件第19页  
MT8930C  
Diagnostic Register cleared. Once full activation is  
achieved the Diagnostic Register can be written to in  
order to enable the various test functions.  
ii) Data  
The data field refers to the Address, Control and  
Information fields defined in the CCITT  
HDLC Transceiver  
recommendations. A valid frame should have a data  
field of at least 16 bits. The first and second byte in  
the data field is the address of the frame.  
The HDLC Transceiver handles the bit oriented  
protocol structure and formats the D-channel as per  
level 2 of the X.25 packet switching protocol defined  
by CCITT. It transmits and receives the packetized  
data (information or control) serially in a format  
shown in Figure 15, while providing data  
transparency by zero insertion and deletion. It  
generates and detects the flags, various link channel  
states and the abort sequence. Further, it provides a  
cyclic redundancy check on the data packets using  
the CCITT defined polynomial. In addition, it can  
recognize a single byte, dual byte or an all call  
address in the received frame. There is also a  
provision to disable the protocol functions and  
provide transparent access to either serial port  
through the microprocessor port. Other features  
provided by the HDLC include, independent port  
selection for transmit and received data (e.g.  
transmit on S-Bus and receive from ST-BUS),  
selectable 16 or 64 kbit/s D-channel as well as an  
HDLC loopback from the transmit to the receive port.  
These features are enabled through the HDLC  
control registers (see Tables 6 and 7).  
iii) Frame Check Sequence (FCS)  
The 16 bits following the data field are the frame  
check sequence bits. The generator polynomial is:  
16 12  
5
G(x)=x +x +x +1  
The transmitter calculates the FCS on all bits of the  
data field and transmits the complement of the FCS  
with most significant bit first. The receiver performs  
a similar computation on all bits of the received data  
but also includes the FCS field. The generating  
polynomial will assure that if the integrity of of the  
transmitted data was maintained, the remainder will  
have a consistent pattern and this can be used to  
identify, with high probability, any bit errors occurred  
during transmission. The error status of the received  
packet is indicated by B7 and B6 bits in the HDLC  
Status Register.  
iv) Zero Insertion and Deletion  
The transmitter, while sending either data from the  
FIFO or the 16 bits FCS, checks the transmission on  
a bit-by-bit basis and inserts a ZERO after every  
sequence of five contiguous ONEs (including the last  
five bits of FCS) to ensure that the flag sequence is  
not imitated. Similarly the receiver examines the  
incoming frame content and discards any ZERO  
directly following the five contiguous ONEs.  
HDLC Frame Format  
All frames start with an opening flag and end with a  
closing flag as shown in Figure 15. Between these  
two flags, a frame contains the data and the frame  
check sequence (FCS).  
v) Abort  
FLAG  
DATA FIELD  
FCS  
FLAG  
One  
Byte  
n Bytes  
(n 2)  
Two  
Bytes  
One  
Byte  
The transmitter aborts a frame by sending a zero  
followed by seven consecutive ONEs. The FA bit in  
the HDLC Control Register 2 along with a write to the  
HDLC Transmit FIFO enables the transmission of an  
abort sequence instead of the byte written to the  
register (to have a valid abort there must be at least  
two bytes in the packet). On the receive side, a  
frame abort is defined as seven or more contiguous  
ONEs occurring after the start flag and before the  
end flag of a packet. An interrupt can be generated  
on reception of the abort sequence using FA bit in  
the HDLC Interrupt Mask/Vector Registers (refer to  
Tables 9 and 10).  
Figure 15 - Frame Format  
i) Flag  
The flag is a unique pattern of 8 bits (01111110)  
defining the frame boundary. The transmit section  
generates the flags and appends them automatically  
to the frame to be transmitted. The receive section  
searches the incoming packets for flags on a  
bit-by-bit  
basis  
and  
establishes  
frame  
synchronization. The flags are used only to identify  
and synchronize the received frame and are not  
transferred to the FIFO.  
9-47