F
L B1 B1 B1 B1 B1 B1 B1 B1 E D0 A Fa N B2 B2 B2 B2 B2 B2 B2 B2 E D1 M
B1 B1 B1 B1 B1 B1 B1 B1 E
D0 S
B2 B2 B2 B2 B2 B2 B2 B2 E
D1 L
F
L
B1 B1 B1 B1 B1
NT to TE
F0b
N
T
DSTi
X
M
T
62.5
µs
62.5
µs
HALF
Input
NDA
T
E
F0b
R
C
V
DSTo
HALF
Output
B2 L D1 L
F
L
B1 B1 B1 B1 B1 B1 B1 B1 L
D0 L
Fa L
B2 B2 B2 B2 B2 B2 B2 B2 L D1 L
B1 B1 B1 B1 B1 B1 B1 B1 L
D0 L
B2 B2 B2 B2 B2 B2 B2 B2 L
D1 L
F
L
B1 B1 B1
TE to NT
F0b
T
E
DSTi
X
M
T
62.5
µs
HALF
Output
62.5
µs
NDA
N
T
F0b
R
C
V
DSTo
HALF
Input
A = Activation bit
M = Multiframing bit
S = S-channel bit
Note: Shaded areas reveal data mapping
Fa & N (NT to TE) = Auxiliary framing bits
Fa (TE to NT) = Auxiliary framing bit or Q-channel bit
B1 = Bit within B1-channel
B2 = Bit within B2-channel
F = Framing bit
L = DC balancing bit
D = Bit within D-channel
E = D-echo channel bit
MT8930C
9-39
Figure 5 - S-Bus Frame Structure and Functional Timing
MITEL [ MITEL NETWORKS CORPORATION ]
