MT8930C
ST-BUS Clock
ST-BUS
Stream
Active on
Channel 0 - 3
MT8930C
NT
System
Frame Pulse
F0b
F0od
Active on
Channels 4 - 7
MT8930C
NT
F0b
F0od
Active on
Channels 8 - 11
MT8930C
NT
F0b
F0od
Active on
Channels 12 - 15
MT8930C
NT
F0b
F0od
to TE
to TE
to TE
to TE
Figure 13 - Daisy Chaining the SNIC
V
DD
MT8930C
NT
System
Frame Pulse
to TE
STAR
F0b
DSTi
MT8930C
NT
STAR
F0b
DSTi
DSTo
to TE
Output
ST-BUS Stream
Input
ST-BUS Stream
to TE
MT8930C
NT
STAR
F0b
DSTi
MT8930C
NT
STAR
F0b
DSTi
to TE
Figure 14 - NT in Star Configuration
Up to eight SNICs in NT mode with physically
independent S-Busses can be connected in parallel
to realize a star configuration, as shown in Figure 14.
All devices connected into the star will carry the
same input, thus information is sent to all TEs
simultaneously. The 2B+D data received from every
TE is transmitted to all NTs through the STAR pin.
Consequently, all the DSTo streams will carry
identical 2B+D data reflecting what is being
transmitted by the various TEs.
The flow of data in the direction of S-Bus to ST-BUS
is transparent to the SNIC, regardless of the state
machine status. On the other hand, the flow of data
in the direction of ST-BUS to S-Bus becomes
transparent only after the state machine is in the
active state (IS0, IS1=1,1), in case of an NT, or in the
synchronization state (IS0, IS1=1), in case of a TE.
Intel multiplexed bus signals and timing.
The
MOTEL
circuit
(MOtorola
and
InTEL
Compatible bus) uses the level of the DS/RD pin
at the rising edge
of AS/ALE to select the
appropriate bus timing. If DS/RD is low at the
rising edge of AS/ALE (refer Fig. 26) then Motorola
bus timing is selected. Conversely, if DS/RD is
high at the rising edge of AS/ALE (refer Figs. 24 &
25), then Intel bus timing is selected. This has the
effect of redefining the microprocessor port
transparently to the user.
In this mode, the user has the option of writing to the
C-channel Control or Diagnostic Register through
the parallel port interface or through the C-channel
on DSTi. Bit 0 of the Master Control Register
provides this option.
The parallel port on the SNIC allows complete
control of the HDLC transceiver and access to all
data, control and status registers. The internal
registers (defined in Table 2) can be accessed
through the microprocessor port only when the
Cmode pin is held high. Reading these registers
allows the microprocessor to monitor incoming data
on the S or ST-BUS without interrupting the normal
data flow.
Microprocessor/Control Interface
The parallel port on the SNIC operates as either a
general purpose microprocessor interface or as a
hardwired control port.
In microprocessor control mode (Cmode = 1), the
parallel port is compatible with either Motorola or
9-45
MITEL [ MITEL NETWORKS CORPORATION ]
