MT8910-1
Preliminary Information
Bit 2 of Control Register 1, START/STOP, provides a
mechanism to allow the user to initiate a line
activation or deactivation. This bit is edge sensitive
with a low to high transition requesting an activation,
of a +3 or +1 symbol once every 1.5 ms. This will
generate pulses that can be used for template
measurements. The Insertion Loss Measurement
(ILM) test signal is a scrambled all 1s 2B1Q coded
signal which contain both the SW and ISW. This test
signal can be used to make insertion loss
measurements over the DSL loop. Lastly, the DSLIC
can be placed into a quiet mode to allow a Remote
Test Unit (RTU) to perform impulse noise, crosstalk
and other transient impairment measurements as
described in the ANSI "ISDN Management - Basic
Rate Physical Layer".
and
a
high to low transition requesting
a
deactivation.
The activation and deactivation
procedure will follow the protocol defined in the ANSI
T1.601-1988. The activation request will only be
recognized if the transceiver is in a full reset state.
Any activation attempt while the transceiver is in any
other state will be ignored.
Similarly, any
deactivation request generated while the transceiver
is not in the active state will be ignored.
Bit 3 of Control Register 2 (ADCGAIN) controls the
gain value of the A/D converter. This function can be
used to introduce more gain in the receive path when
the transceiver is being used over long loops.
Control Register 2
Setting CRS0=1 and CRS1=0 routes the C-channel
to Control Register 2 allowing access to the
functions described in Table 3. These bits are further
described below.
Bit 2 of Control Register 2 (MSWAP) may be used
when the DSLIC is operating as an LT within a line
card application. The mode swap feature has the
effect of changing the scrambling polynomial and
activation state machine such that it can simulate the
operation of an NT transceiver. This allows a
transmission test between two devices on the same
line card. (For this function to work properly, the
input clocks to the two devices must be frequency
locked.)
Bits 7 to 4 of Control Register 2 (DS4 to DS1)
provide access to the multiple diagnostic features
supported on the DSLIC as outlined in Table 3.
These include the per-channel loopbacks at the
system interface as well as a loopback at the line
interface.
Along with the extensive loopback
capabilities, the DSLIC also allows the generation of
multiple signals which can be used during
qualification and servicing of a DSL. The isolated
pulse test diagnostics signal causes the transmission
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SRS1
SRS0
TxSFB
BSWAP
CCRC
START/STOP
CRS1
CRS0
Bit
Name
Description
7,6
SRS1, SRS0 Status Register Select. Selects which of the four status registers will be output in the next ST-
BUS frame.
5
TxSFB
Transmit Superframe Reset. In LT mode, transition from a 1 to a 0 on this bit resets the
superframe counters in the next ST-BUS frame in order to establish the transmit superframe
boundary. If the external pin is being used to set the superframe boundary this bit can be held
high or low. Not used in NT mode.
4
BSWAP
CCRC
When this bit is set to 1, the location of the B1 channel on the ST-BUS is swapped with the
location of the B2 channel. This affects both directions of the ST-BUS.
3
2
Corrupt CRC. When set to 1, the 12 bit CRC transmitted on the line is corrupted.
START/STOP A low to high transition while the transceiver is in the full reset state will initiate one activation
attempt. A high to low transition of this bit while the transceiver is in the active state will initiate a
deactivation procedure. During start-up, 2B+D channels should remain set to 0 or 1 until
transparency of network is achieved (indicated by act=1).
1, 0
CRS1, CRS0 Control Register Select 1 and 0. Must be set to 0, 0 to address Control Register 1.
Table 2. Control Register 1
9-14
MITEL [ MITEL NETWORKS CORPORATION ]
