MT8910-1
Functional Description
The MT8910-1 Digital Subscriber Line Interface
Circuit (DSLIC) is a high performance, full duplex
transceiver which provides a complete interface to
the U-reference point as specified in ANSI T1.601-
1988. Operating in either master Line Terminator
(LT) mode or slave Network Terminator (NT) mode,
the DSLIC can be configured to operate at either end
of the Digital Subscriber Line (DSL). The DSLIC
supports full duplex transmission of a 2B + D-
channel format at 160 kbit/s over a single twisted
pair with about 40 dB of loop attenuation at 40 kHz.
To achieve this transmission performance, the
DSLIC uses a 2B1Q line code which is a four level
pulse amplitude modulated (PAM) signal with no
redundancy. This line code was approved by the
American National Standards Institute technical
committee T1E1. Using this line code, two binary
bits are converted into one four level quaternary
symbol. This results in an effective baud rate
reduction from 160 to 80 kbaud/s allowing the
transmission to benefit from reduced line attenuation
and improved immunity to near end crosstalk
(NEXT).
To complement the performance of the 2B1Q line
code, the DSLIC uses an advanced echo cancelling
hybrid (ECH) technique, by means of a transversal
filter, that provides greater than 60 dB of echo
cancellation.
This cancellation, along with all
equalization, is performed in the digital domain using
dedicated DSP hardware. Since a digital transversal
echo canceller gives a linear representation of the
echo, the MT8910-1 also has a non-linear echo
canceller which works in parallel with the transversal
filter to compensate for non-linearities in the transmit
path and the passive line termination. In addition, a
jitter compensator is used to correct errors in the
echo estimates which are sourced from corrections
in the received timebase. The jitter compensator will
interact directly with the echo taps in the transversal
filter.
A block diagram of the DSLIC is shown in Figure 1.
The DSLIC has two ports consisting of a serial
system interface (Mitel's standard ST-BUS), and a
line port which interfaces directly to the single
twisted pair via a passive termination hybrid and a
line pulse transformer.
The two B-channels and the D-channel to be
transmitted on the line are input to the DSLIC (on the
ST-BUS) into the transmit interface block. The sync
word and maintenance bits are added to the data
which is then formatted, scrambled and digitally
encoded into 2B1Q symbols.
This digital
representation is passed through a finite impulse
9-6
Preliminary Information
response filter which converts the digital
representation into an analog waveform. The
transmitted pulse is then passed through a
smoothing filter whose output is passed to a
differential line driver which is driving the line through
a passive hybrid network and line pulse transformer.
On the receive side, the pre-cancelled signal drives
a balanced receiver which feeds the input to an over-
sampled second-order delta sigma A/D converter.
The digital representation of the received signal
yields a Pulse Density Modulated (PDM) stream
which is digitally filtered and decimated to the 80 kHz
baseband. Intersymbol interference (ISI) introduced
by the loop is cancelled by a decision feedback
equalizer. This is achieved by taking a convolution
of the received pulse with the estimated impulse
response of the loop. The cancellation of ISI is
performed in parallel with the echo cancellation.
Estimated received echo is obtained by taking the
convolution of the transmit signal with the estimated
impulse response of the loop. Feedback from the
jitter compensator and the non-linear corrector
interact with the coefficients of the echo canceller to
reduce the error introduced by jitter and non-
linearities in the analog circuitry. The output of all
these blocks is summed together and the result is
the received data which is passed through a decoder
and descrambler before being sent out in TDM
bursts on the ST-BUS.
Line Port
The DSLIC interfaces to the U-reference point as
defined in the ISDN Basic Access Reference model.
As such, the transceiver transfers full duplex, time
division multiplexed data at 160 kbit/s. This includes
two 64 kbit/s PCM voice or data channels (B-
channels), a 16 kbit/s signalling channel (D-channel)
and 16 kbit/s for synchronization and overhead.
The two 64 kbit/s channels are defined as the B1-
and B2-channels and they carry subscriber
information such as digitally encoded voice, circuit
switched data or packet switched data. The DSLIC
will transfer both B-channels transparently from the
ST-BUS port to the line port and vice versa once the
device has acquired superframe synchronization.
The 16 kbit/s D-channel is primarily intended to carry
signalling information for circuit switching the B-
channels through the ISDN network. The D-channel
can optionally carry packetized information and
telemetry services. The D-channel is transmitted
transparently through the DSLIC from the ST-BUS
port to the line port and vice versa once the device
has acquired superframe synchronization. It is to be
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