MT88V32
GND
Y0
GND
GND
X0
GND
X1
GND
X2
GND
X3
Preliminary Information
Y1
GND
Y2
GND
Y3
GND
Y4
GND
Y5
GND
Y6
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
GND
Y7
GND
VEE
IC*
VDD
VSS
AX1
AX0
AY2
NC
GND
NC
MR
STROBE2
STROBE1
R/W
CS
DATA
AY0
AY1
NC
* Connects toV
EE
Figure 2 - Pin Connections
Pin Description
Pin #*
1, 3, 4, 6,
8, 10,
12, 14,
16, 18,
20, 39,
41, 43
2, 44,
42, 40
5, 7,
9, 11,
13, 15,
17, 19
21
22
23
24
25, 26
27, 30,31
28, 29
32
Name
GND
Description
Analog Ground.
Connect to system ground for crosstalk noise isolation. Pins 3 and 39
are not bonded internally.
X0, X1,
X2, X3
Y0, Y1,
Y2, Y3
Y4, Y5,
Y6, Y7
V
EE
IC
V
DD
V
SS
AX1,AX0
AY2-AY0
NC
DATA
Analog Lines (input/output).
Analog Lines (input/output).
Negative Analog Power Supply.
Internal Connection.
Positive Power Supply.
Digital Ground Reference.
X0-X3 I/O Address Select (inputs).
Y0-Y7 I/O Address Select (inputs).
No Connection.
DATA (input/output).
When input, a logic high will close the selected switch and a logic
low will open the selected switch. When output, a logic high indicates a closed switch
and a logic low indicates an opened switch.
Chip Select (input).
Active low.
READ/WRITE Control (input).
When high the DATA pin is an output (for reading from
second stage latch); when low the DATA pin is an input (for writing to first stage latch).
33
34
35
CS
R/W
STROBE1
STROBE 1 (input).
Modifies memory content of first stage latch as determined by the
addess and data lines, but does not change the switch array configuration of entire
switch array. Active low.
STROBE2
STROBE 2 (input).
Transfers memory content of first stage latch to the second stage
latch and hence, changes the configuration of entire switch array. Active low.
MR
NC
MASTER RESET (input).
Used to reset the first and second stage latches. Active low.
No Connection.
36
37
38
3-52
MITEL [ MITEL NETWORKS CORPORATION ]
