MT88L89
24
23
22
21
20
19
18
17
16
15
14
13
Advance Information
GS
NC
IN-
IN+
VDD
St/GT
EST
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W/WR
CS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
DS/RD
RS0
20 PIN CERDIP/PLASTIC DIP/SOIC
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
20
1
2
3
4
5
6
7
24
1
2
3
4
5
6
7
28
1
2
4
6
7
8
9
Name
IN+
IN-
GS
V
Ref
V
SS
OSC1
OSC2
Non-inverting
op-amp input.
Inverting
op-amp input.
Gain Select.
Gives access to output of front end differential amplifier for connection of
feedback resistor.
Reference Voltage
output (V
DD
/2).
Ground (0V).
Oscillator
input. This pin can also be driven directly by an external clock.
Oscillator
output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
Output from internal DTMF transmitter.
(Motorola)
Read/Write
or (Intel)
Write
microprocessor input. TTL compatible.
Chip Select
input. This signal must be qualified externally by either address strobe
(AS), valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.
Register Select
input. Refer to Table 3 for bit interpretation. TTL compatible.
Description
8
9
10
11
12
13
10
11
12
13
14
15
12
13
14
15
17
18
TONE
R/W
(WR)
CS
RS0
DS
(RD)
(Motorola)
Data Strobe
or (Intel)
Read
microprocessor input. Activity on this input is
only required when the device is being accessed. TTL compatible.
IRQ/CP
Interrupt Request/Call Progress
(open drain) output. In interrupt mode, this output
goes low when a valid DTMF tone burst has been transmitted or received. In call
progress mode, this pin will output a rectangular signal representative of the input signal
applied at the input op-amp. The input signal must be within the bandwidth limits of the
call progress filter, see Figure 8.
D0-D3
ESt
Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
(Intel). TTL compatible.
Early Steering
output. Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt
to return to a logic low.
Steering Input/Guard Time
output (bidirectional). A voltage greater than V
TSt
detected
at St causes the device to register the detected tone pair and update the output latch. A
voltage less than V
TSt
frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage
on St.
14- 18- 19-
17 21 22
18
22
26
19
23
27
St/GT
4-126
TONE
R/W
CS
RS0
NC
DS/RD
IRQ/CP
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W/WR
CS
1
2
3
4
5
6
7
8
9
10
11
12
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
DS/RD
RS0
4
3
2
1
28
27
26
•
12
13
14
15
16
17
18
NC
VRef
VSS
OSC1
OSC2
NC
NC
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC
NC
NC
D3
D2
D1
D0
28 PIN PLCC
MITEL [ MITEL NETWORKS CORPORATION ]
