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activated. CD is released when there is no activity at
the FSK bandpass filter output for 10ms.
When CD is inactive (high), the raw output of the
FSK demodulator is ignored by the internal data
timing recovery circuit. In mode 0 the DATA, DCLK
and DR pins are forced high. In mode 1 the output
shift register is not updated and DR is high; if DCLK
is clocked, DATA is undefined.
Note that signals such as speech, CAS and DTMF
tones also lie in the FSK frequency band and the
carrier detector may be activated by these signals.
They will be demodulated and presented as data. To
avoid the false data, the MT88E45 should be put into
CAS or power down mode when FSK is not
expected. Ringing, on the other hand, does not pose
a problem as it is ignored by the carrier detector.
MT88E45
In power down mode both input op-amps, V
REF
and
the oscillator are non functional. DCLK becomes an
input because to select the power down state CB0 is
1 which will select FSK interface mode 1. If the
application uses FSK interface mode 0 and the
MT88E45 needs to be powered down then a pull
down resistor should be added at the DCLK pin to
define its state during power down (R15 in Figure 7).
When the MT88E45 is powered down DATA, DR/
STD, CD are high; EST and ST/GT are low.
To reduce the operating current an Intelligent Power
Down feature has been incorporated. When FSK is
selected, the CAS detector is powered down. When
CAS is selected the FSK demodulator is powered
down. The two input op-amps are not affected and
both will remain operational.
Oscillator
Interrupt
The DR/STD output can be used to interrupt a
microcontroller. When the MT88E45 is the only
interrupt source, DR/STD can be connected directly
to the microcontroller’s interrupt input. Figure 9
shows the necessary connections when the
MT88E45 is one of many interrupt sources. The
diodes and resistors implement a wired-or so that the
microcontroller is interrupted (INT low active or
falling edge triggered) when one or more of INT1,
INT2 or DR/STD is low. The microcontroller can
determine which one of DR/STD
,
INT1
or
INT2
caused the interrupt by reading them into an input
port.
When system power is first applied and CB0/1/2
have already been configured to select CAS
detection, DR/STD will power up as logic low. This is
because there is no charge across the ST/GT
capacitor in Figure 5, hence ST/GT is at Vdd which
causes STD to be low. If DR/STD is used to interrupt
a microcontroller the interrupt will not clear until the
capacitor has charged up. Therefore upon initial
power up the microcontroller should ignore this
interrupt source until there is sufficient time to
charge the capacitor. Alternatively, the MT88E45 can
be put into power down mode: DR/STD goes high
and clears the interrupt, ST/GT goes low and the
capacitor will charge up quickly.
The MT88E45 requires a 3.579545MHz crystal or
ceramic resonator to generate its oscillator clock. To
meet the CAS detection frequency tolerance
specifications the crystal or resonator must have a
0.1% frequency tolerance. The crystal specification
is as follows: (e.g. CTS MP036S)
Frequency:
Frequency Tolerance:
Resonance Mode:
Load Capacitance:
Maximum Series
Resistance:
Maximum Drive Level:
3.579545MHz
±
0.1% (over temperature
range of the application)
Parallel
18pF
150Ω
2mW
Alternatively an external clock source can be used.
In which case the OSC1 pin should be driven directly
from a CMOS buffer and the OSC2 pin left open.
For 5V+/-10% applications any number of
MT88E45’s can be connected as shown in Figure 6
so that only one crystal is required.
MT88E45
OSC1
OSC2
MT88E45
OSC1
OSC2
MT88E45
OSC1
OSC2
Power Down
3.579545 MHz
to the
next MT88E45
(For 5V+/-10% applications only)
The MT88E45 can be powered down to consume
virtually no power supply current via a state of the
CB0/1/2 pins. Momentary transition of CB0/1/2 into
the power down code will not activate power down.
Figure 6 - Common Crystal Connection
11
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