MT8889C/MT8889C-1
BIT
NAME
STATUS FLAG SET
STATUS FLAG CLEARED
b0
IRQ
Interrupt has occurred. Bit one
(b1) or bit two (b2) is set.
Interrupt is inactive. Cleared after
Status Register is read.
b1
TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
Pause duration has terminated
and transmitter is ready for new
data.
Cleared after Status Register is
read or when in non-burst mode.
b2
b3
RECEIVE DATA REGISTER
FULL
Valid data is in the Receive Data
Register.
Cleared after Status Register is
read.
DELAYED STEERING
Set upon the valid detection of
the absence of a DTMF signal.
Cleared upon the detection of a
valid DTMF signal.
Table 8. Status Register Description
VDD
C3
MT8889C/MT8889C-1
VDD
St/GT
ESt
IN+
C1
R1
C2
DTMF/CP
INPUT
IN-
R4
GS
R3
R2
D3
VRef
VSS
D2
X-tal
D1
OSC1
OSC2
TONE
R/W/WR
CS
D0
To µP
or µC
DTMF
OUTPUT
IRQ/CP
DS/RD
RS0
RL
Notes:
R1, R2 = 100 kΩ 1%
R3 = 374 Ω 1%
R4 = 3.3 kΩ 10%
RL = 10 k Ω (min.)
C1 = 100 nF 5%
C2 = 100 nF 5%
* Microprocessor based systems can inject undesirable noise into the supply rails.
The performance of the MT8889C/MT8889C-1 can be optimized by keeping
noise on the supply rails to a minimum. The decoupling capacitor (C3) should be
connected close to the device and ground loops should be avoided.
C3 = 100 nF 10%*
X-tal = 3.579545 MHz
Figure 13 - Application Circuit (Single-Ended Input)
4-117
MITEL [ MITEL NETWORKS CORPORATION ]
