MT8888C/MT8888C-1
20
19
18
17
16
15
14
13
12
11
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W
CS
1
2
3
4
5
6
7
8
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W
CS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
9
10
9
RD
RS0
10
11
12
RD
RS0
20 PIN CERDIP/PLASTIC DIP/SOIC
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
20 24
1
2
3
1
2
3
IN+ Non-inverting op-amp input.
IN-
GS
Inverting op-amp input.
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
4
5
6
7
4
5
6
7
V
Reference Voltage output (V /2).
Ref
DD
V
Ground (0V).
SS
OSC1 Oscillator input. This pin can also be driven directly by an external clock.
OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes
the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
8
9
10 TONE Output from internal DTMF transmitter.
11 WR Write microprocessor input. TTL compatible.
10 12
CS
Chip Select input. Active Low. This signal must be qualified externally by address latch
enable (ALE) signal, see Figure 12.
11 13
12 14
13 15
RS0 Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.
RD Read microprocessor input. TTL compatible.
IRQ/ Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes
CP
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter, see
Figure 8.
14- 18- D0-D3 Microprocessor Data Bus. High impedance when CS = 1 or RD = 1.
17 21
TTL compatible.
18 22
ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
19 23 St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than V
detected at St
TSt
causes the device to register the detected tone pair and update the output latch. A voltage
less than V frees the device to accept a new tone pair. The GT output acts to reset the
TSt
external steering time-constant; its state is a function of ESt and the voltage on St.
20 24
V
Positive power supply (5V typ.).
No Connection.
DD
8,9
16,17
NC
4-92
MITEL [ MITEL NETWORKS CORPORATION ]
