MT8888C/MT8888C-1
BIT
b0
b1
NAME
IRQ
TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
RECEIVE DATA REGISTER
FULL
DELAYED STEERING
STATUS FLAG SET
Interrupt has occurred. Bit one
(b1) or bit two (b2) is set.
Pause duration has terminated
and transmitter is ready for new
data.
Valid data is in the Receive Data
Register.
Set upon the valid detection of
the absence of a DTMF signal.
STATUS FLAG CLEARED
Interrupt is inactive. Cleared after
Status Register is read.
Cleared after Status Register is
read or when in non-burst mode.
Cleared after Status Register is
read.
Cleared upon the detection of a
valid DTMF signal.
b2
b3
Table 8
.
Status Register Description
8031/8051
8080/8085
A8-A15
A8
MT8888C/MT8888C-1
CS
RS0
D0-D3
PO
RD
WR
RD
WR
Figure 12 - MT8888C Interface Connections for Various Intel Micros
V
DD
MT8888C/MT8888C-1
C1
DTMF/CP
INPUT
R1
IN+
IN-
GS
R2
VRef
VSS
X-tal
OSC1
OSC2
DTMF
OUTPUT
R
L
TONE
WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
RD
RS0
To
µP
or
µC
R3
C2
R4
C3
Notes:
R1, R2 = 100 kΩ 1%
R3 = 374
Ω
1%
R4 = 3.3 kΩ 10%
R
L
= 10 k
Ω
(min.)
C1 = 100 nF 5%
C2 = 100 nF 5%
C3 = 100 nF 10%*
X-tal = 3.579545 MHz
* Microprocessor based systems can inject undesirable noise into the supply rails.
The performance of the MT8888C/MT8888C-1 can be optimized by keeping
noise on the supply rails to a minimum. The decoupling capacitor (C3) should be
connected close to the device and ground loops should be avoided.
Figure 13 - Application Circuit (Single-Ended Input)
4-100
MITEL [ MITEL NETWORKS CORPORATION ]
