MT8880C/MT8880C-1
ISO
2
-CMOS
GS
NC
IN-
IN+
VDD
St/GT
EST
20 PIN CERDIP/PLASTIC DIP/SOIC
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
20 24 28
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
1
2
4
6
7
Name
IN+ Non-inverting op-amp input.
IN-
GS
Inverting op-amp input.
Gain Select.
Gives access to output of front end differential amplifier for connection of
feedback resistor.
Description
V
Ref
Reference Voltage
output, nominally V
DD
/2 is used to bias inputs at mid-rail (see Fig. 13).
V
SS
Ground input (0V).
8 OSC1 DTMF clock/oscillator input.
9 OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the
internal oscillator circuit. Leave open circuit when OSC1 is clock input.
R/W
Read/Write
input. Controls the direction of data transfer to and from the MPU and the
transceiver registers. TTL compatible.
CS
Φ2
Chip Select,
TTL input (CS=0 to select the chip).
System Clock
input. TTL compatible.
N.B.
Φ2
clock input need not be active when the
device is not being accessed.
RS0
Register Select
input. See register decode table. TTL compatible.
10 12 TONE
Tone
output (DTMF or single tone).
11 13
10 12 14
11 13 15
12 14 17
13 15 18 IRQ/
Interrupt Request to MPU
(open drain output). Also, when call progress (CP) mode has
CP been selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal
representative of the input signal applied at the input op-amp. The input signal must be within
the bandwidth limits of the call progress filter. See Figure 8.
14- 18- 19- D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS = 1 or
Φ2
is low.
17 21 22
18 22 26
ESt
Early Steering
output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to
a logic low.
19 23 27 St/GT
Steering Input/Guard Time
output (bidirectional). A voltage greater than V
TSt
detected at St
causes the device to register the detected tone pair and update the output latch. A voltage
less than V
TSt
frees the device to accept a new tone pair. The GT output acts to reset the
external steering time-constant; its state is a function of ESt and the voltage on St.
20 24 28
8,9
16,
17
V
DD
Positive power supply input (+5V typical).
NC
No Connection.
3,5,
10,
11,
16,
23-
25
4-34
TONE
R/W
CS
RS0
NC
Φ2
IRQ/CP
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W
CS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
Φ2
RS0
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W
CS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
Φ2
RS0
4
3
2
1
28
27
26
•
12
13
14
15
16
17
18
NC
VRef
VSS
OSC1
OSC2
NC
NC
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC
NC
NC
D3
D2
D1
D0
28 PIN PLCC
MITEL [ MITEL NETWORKS CORPORATION ]
