ISO2-CMOS MT8880C/MT8880C-1
AC Electrical Characteristics† - Call Progress - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max
Units
Notes*
@ -25 dBm
1
2
3
4
5
Lower freq. (ACCEPT)
Upper freq. (ACCEPT)
Lower freq. (REJECT)
Upper freq. (REJECT)
f
320
510
290
540
Hz
Hz
LA
f
@ -25 dBm
@ -25 dBm
@ -25 dBm
HA
f
Hz
LR
f
Hz
HR
Call progress tone detect level
(total power)
-30
dBm
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing
* See “Notes” AC Electrical Characteristics Tables
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max Units
Conditions
ms Note 12
ms Note 12
1
2
Tone present detect time
Tone absent detect time
Tone duration accept
Tone duration reject
Interdigit pause accept
Interdigit pause reject
Delay St to b3
t
3
11
4
14
8.5
40
DP
t
0.5
DA
#
#
#
#
3
t
t
ms User adjustable
ms User adjustable
ms User adjustable
ms User adjustable
µs
REC
REC
4
20
20
R
X
5
t
40
ID
6
t
DO
7
t
13
8
PStb3
PStRX
8
Delay St to RX -RX
t
µs
0
3
9
Tone burst duration
t
50
50
52
52
ms DTMF mode
ms DTMF mode
BST
10
11
12
13
14
15
16
Tone pause duration
t
PS
T
X
Tone burst duration (extended)
Tone pause duration (extended)
High group output level
Low group output level
Pre-emphasis
t
100
100
-6.1
-8.1
104
104
-2.1
-4.1
3
ms Call Progress mode
ms Call Progress mode
BSTE
t
PSE
V
dBm R =10kΩ
L
HOUT
T
O
N
E
V
dBm R =10kΩ
L
LOUT
dB
2
dB
dB
R =10kΩ
P
L
Output distortion (Single Tone)
THD
-35
25 kHz Bandwidth
O
U
T
R =10kΩ
L
17
18
19
20
21
22
23
24
25
26
27
Frequency deviation
f
±0.7 ±1.5
%
kΩ
ns
ns
ns
ns
ns
ns
ns
ns
ns
f =3.579545 MHz
D
C
Output load resistance
Φ2 cycle period
R
10
50
250
LT
t
CYC
M
P
U
Φ2 high pulse width
t
115
CH
Φ2 low pulse width
t
110
CL
I
Φ2 rise and fall time
t
t
25
R, F
N
T
E
R
F
A
C
E
Address, R/W hold time
Address, R/W setup time (before Φ2)
Data hold time (read)
Φ2 to valid data delay (read)
Data setup time (write)
t
t
26
23
22
AH, RWH
t
t
AS, RWS
t
t
*
DHR
DDR
DSW
100
200 pF load
t
45
4-47
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