MT8870D/MT8870D-1
ISO
2
-CMOS
AC Electrical Characteristics
- V
DD
=5.0V±5%, V
SS
=0V, -40°C
≤
To
≤
+85°C , using Test Circuit shown in Figure 10.
Characteristics
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
C
L
O
C
K
O
U
T
P
U
T
S
T
I
M
I
N
G
Sym
t
DP
t
DA
t
REC
t
REC
t
ID
t
DO
t
PQ
t
PStD
t
QStD
t
PTE
t
PTD
t
PU
t
PD
f
C
t
LHCL
t
HLCL
DC
CL
C
LO
Min
5
0.5
Typ
‡
11
4
Max
14
8.5
40
Units
ms
ms
ms
ms
Conditions
Note 1
Note 1
Note 2
Note 2
Note 2
Note 2
TOE=V
DD
TOE=V
DD
TOE=V
DD
load of 10 kΩ,
50 pF
load of 10 kΩ,
50 pF
Note 3
Tone present detect time
Tone absent detect time
Tone duration accept
Tone duration reject
Interdigit pause accept
Interdigit pause reject
Propagation delay (St to Q)
Propagation delay (St to StD)
Output data set up (Q to StD)
Propagation delay (TOE to Q ENABLE)
Propagation delay (TOE to Q DISABLE)
Power-up time
Power-down time
Crystal/clock frequency
Clock input rise time
Clock input fall time
Clock input duty cycle
Capacitive load (OSC2)
20
40
20
8
12
3.4
50
300
30
20
3.5759
3.5795
3.5831
110
110
40
50
60
30
11
16
ms
ms
µs
µs
µs
ns
ns
ms
ms
MHz
ns
ns
%
pF
P
D
W
N
Ext. clock
Ext. clock
Ext. clock
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES:
1.
Used for guard-time calculation purposes only.
2.
These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums
are recommendations based upon network requirements.
3.
With valid tone present at input, t
PU
equals time from PDWN going low until ESt going high.
V
DD
C
1
DTMF
Input
R
1
C
2
MT8870D/MT8870D-1
IN+
IN-
R
2
GS
V
Ref
INH
PDWN
OSC 1
X-tal
OSC 2
V
SS
V
DD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
NOTES:
R
1
,R
2
=100KΩ
±
1%
R
3
=300KΩ
±
1%
C
1
,C
2
=100 nF
±
5%
X-tal=3.579545 MHz
±
0.1%
R
3
Figure 10 - Single-Ended Input Configuration
4-20
MITEL [ MITEL NETWORKS CORPORATION ]
