MT8814
ISO-CMOS
t
CSS
50%
t
CSH
50%
t
RPW
50%
50%
CS
RESET
t
SPW
50%
t
AS
50%
50%
STROBE
ADDRESS
50%
50%
t
AH
DATA
50%
t
DS
ON
t
DH
50%
SWITCH*
OFF
t
D
* See Appendix, Fig. A.7 for switching waveform
t
S
t
R
t
R
Figure 3 - Control Memory Timing Diagram
AX0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
AX1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
↓
0
0
↓
0
0
↓
0
0
↓
0
0
↓
0
0
↓
0
0
↓
0
AX2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
AX3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
1
AY0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
↓
1
0
↓
0
1
↓
1
0
↓
0
1
↓
1
0
↓
0
1
↓
1
AY1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↓
0
1
↓
1
1
↓
1
0
↓
0
0
↓
0
1
↓
1
1
↓
1
AY2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↓
0
0
↓
0
0
↓
0
1
↓
1
1
↓
1
1
↓
1
1
↓
1
Connection
X0-Y0
X1-Y0
X2-Y0
X3-Y0
X4-Y0
X5-Y0
No Connection
1
No Connection
1
X6-Y0
X7-Y0
X8-Y0
X9-Y0
X10-Y0
X11-Y0
No Connection
No Connection
X0-Y1
↓↓
X11-Y1
X0-Y2
↓↓
X11-Y2
X0-Y3
↓↓
X11-Y3
X0-Y4
↓↓
X11-Y4
X0-Y5
↓↓
X11-Y5
X0-Y6
↓↓
X11-Y6
X0-Y7
↓↓
X11-Y7
Table 1. Address Decode Truth Table
This address has no effect on device status.
3-38