MT8809
ISO-CMOS
t
CSS
t
CSH
50%
t
RPW
CS
50%
RESET
STROBE
50%
t
SPW
50%
50%
50%
50%
ADDRESS
50%
t
AS
50%
t
AH
50%
t
DS
t
DH
50%
DATA
ON
SWITCH*
OFF
t
D
t
S
t
R
t
R
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
AY2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AY1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AY0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
AX2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
AX1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
AX0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Connection
X0
X1
X2
X3
X4
X5
X6
X7
X0
X1
X2
X3
X4
X5
X6
X7
X0
X1
X2
X3
X4
X5
X6
X7
X0
X1
X2
X3
X4
X5
X6
X7
Y0
Y0
Y0
Y0
Y0
Y0
Y0
Y0
Y1
Y1
Y1
Y1
Y1
Y1
Y1
Y1
Y2
Y2
Y2
Y2
Y2
Y2
Y2
Y2
Y3
Y3
Y3
Y3
Y3
Y3
Y3
Y3
AY2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AY1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AY0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
AX2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
AX1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
AX0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Connection
X0
X1
X2
X3
X4
X5
X6
X7
X0
X1
X2
X3
X4
X5
X6
X7
X0
X1
X2
X3
X4
X5
X6
X7
X0
X1
X2
X3
X4
X5
X6
X7
Y4
Y4
Y4
Y4
Y4
Y4
Y4
Y4
Y5
Y5
Y5
Y5
Y5
Y5
Y5
Y5
Y6
Y6
Y6
Y6
Y6
Y6
Y6
Y6
Y7
Y7
Y7
Y7
Y7
Y7
Y7
Y7
Table 1. Address Decode Truth Table
3-26