MT8804A
CMOS
50%
MR
t
AEW
50%
t
AS
ADDRESS
50%
50%
t
AH
D0-D3
50%
t
DS
ON
OFF
t
PLH
/t
PHL
t
PAE
t
PLH
/t
PHL
t
MR
t
DH
50%
50%
50%
50%
AE
SWITCH
t
MRR
Figure 6 - Control Memory Timing Diagram
Memory
Reset
MR
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↓
Address
Enable
AE
X
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
↓
Address
A2
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↓
Addressed
Line
A0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
↓
Input Data To Control
Memory
D3
D2
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
↓
Junctors Connected To
Addressed Line
D0
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
↓
A1
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↓
D1
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
↓
J3
J2
J1
J0
ALL
NONE
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L1
↓
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
↓
All Switches "OFF"
No Change of State
•
•
•
•
•
•
•
•
+
+
+
+
+
+
+
+
•
↓
•
•
•
•
+
+
+
+
•
•
•
•
+
+
+
+
•
↓
•
•
+
+
•
•
+
+
•
•
+
+
•
•
+
+
•
↓
•
+
•
+
•
+
•
+
•
+
•
+
•
+
•
+
•
↓
0
0
↓
1
1
↓
0
0
↓
0
1
↓
1
0
↓
L1
L2
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
+
•
↓
+
•
↓
+
•
↓
+
•
↓
0
0
↓
1
1
↓
0
0
↓
1
1
↓
0
1
↓
L2
L3
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
+
•
↓
+
•
↓
+
•
↓
+
•
↓
0
0
↓
1
1
↓
0
1
↓
1
0
↓
1
0
↓
L3
L4
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
+
•
↓
+
•
↓
+
•
↓
+
•
↓
0
0
↓
1
1
↓
1
1
↓
0
0
↓
0
1
↓
L4
L5
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
+
•
↓
+
•
↓
+
•
↓
+
•
↓
0
0
↓
1
1
↓
1
1
↓
0
1
↓
1
0
↓
L5
L6
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
+
•
↓
+
•
↓
+
•
↓
+
•
↓
0
0
↓
1
1
↓
1
1
↓
1
1
↓
0
1
↓
L6
L7
↓
1
0
↓
1
0
↓
1
0
↓
1
0
↓
+
•
↓
+
•
↓
+
•
↓
+
•
↓
0
1
1
1
1
L7
1
1
1
1
+
+
+
+
Table 1 - Address Decode Truth Table
NOTES:
0 - Low Logic Level
1 - High Logic Level
X - Don’t Care Condition
+ - Indicates Connection Between Junctor and Addressed Line
• - Indicates No Connection Between Junctor and Addressed Line
3-8
MITEL [ MITEL NETWORKS CORPORATION ]
