CMOS MT8804A
Functional Description
The MT8804A is a CMOS/LSI 8 X 4 Analog Switch
Array incorporating an 8 X 4 analog switch array,
address decoder, control memory, and digital logic
level converter.
The analog switch array is arranged in 8 rows and 4
columns. The row input/outputs are referred to as
Lines (L0-L7) and the column input/outputs as
Junctors (J0-J3). The crosspoint analog switches
interconnect the lines and junctors when turned “ON”
and provide a high degree of isolation when turned
“OFF”. Interchannel crosstalk is minimal despite the
high density of the analog switch array. The control
memory of the MT8804A can be treated as an 8
word by 4 bit random access memory. The 8 words
are selected by the ADDRESS (A0-A2) inputs
through the on chip address decoder. Data is
presented to the memory via the four DATA inputs
(D0-D3). This data is asynchronously written into the
control memory whenever the ADDRESS ENABLE
(AE) input is HIGH. A HIGH level written into a
memory cell turns the corresponding crosspoint
switch “ON” while a LOW level causes the crosspoint
to turn “OFF”.
Figure 3 - On Resistance vs. Temperature
(Input Signal Voltage=Supply Voltage/2)
V
=5V, V =0V and V =-6V, the control inputs
SS EE
DD
can be driven by a 5V system while the analog
voltages through the crosspoint switches can swing
from +5V to -6V.
Only the crosspoint switches corresponding to the
addressed memory word are affected when data is
written into the memory. The remaining switches
retain their previous states. By establishing
appropriate patterns in the control memory, any
combination of lines and junctors may be
interconnected. A HIGH level on the MASTER
RESET (MR) input returns all memory locations to a
LOW level and turns all crosspoint switches “OFF”
effectively isolating the lines from the junctors. The
digital logic level converters allow the digital input
levels to differ from limits of the analog levels
switched through the array. For example, with
Figure 4 - On Resistance vs. Input Signal Voltage
8x8 Analog/Digital Switch
Two MT8804s configured as shown, implement
an 8 x 8 analog/digital switch. The switch capacity
can be expanded to an M x N array of inputs/
outputs. Expansion in the M dimension is as
shown with the MT8804A lines (L0-L7)
commoned. Expansion in the N dimension is
accomplished by replicating the circuit shown and
connecting the MT8804A junctors (J0-J3) in
common. The address and data control inputs of
the MT8804A’s can be connected in common for
any size and switch provided that the address
enable (AE) inputs are driven individually.
A
particular signal path is connected by setting up
the appropriate signals or the address and data
lines and taking the corresponding address
enable input high. The master reset (MR), when
taken high, disconnects all signal paths.
Figure 5 - 8 x 8 Analog/Digital Switch
3-5
MITEL [ MITEL NETWORKS CORPORATION ]
