MT3170B/71B, MT3270B/71B, MT3370B/71B
MT3370B/71B
VDD
NC
NC
ESt/DStD
NC
ACK
NC
SD
NC
NC
NC
INPUT
PWDN
NC
OSC2
OSC1
VSS
NC
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
NC
VDD
NC
ESt/DStD
NC
ACK
SD
NC
NC
MT3170B/71B
INPUT
PWDN
CLK
VSS
1
2
3
4
8
7
6
5
VDD INPUT
ESt/
DStD OSC2
ACK
SD
OSC1
VSS
MT3270B/71B
1
2
3
4
8
7
6
5
VDD
ESt/
DStD
ACK
SD
NC
INPUT
PWDN
OSC2
NC
OSC1
NC
NC
VSS
MT3370B/71B
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
8 PIN PLASTIC DIP
18 PIN PLASTIC SOIC
20 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
337xB
2
4
6
327xB
1
2
3
317xB
1
-
3
Name
INPUT
OSC2
OSC1
(CLK)
Description
DTMF/CP Input.
Input signal must be AC coupled via capacitor.
Oscillator Output.
Oscillator/Clock Input.
This pin can either be driven by:
1) an external digital clock with defined input logic levels. OSC2
should be left open.
2) connecting a crystal or ceramic resonator between OSC1 and
OSC2 pins.
Ground.
(0V)
Serial Data/Call Progress Output.
This pin serves the dual function
of being the serial data output when clock pulses are applied after
validation of DTMF signal, and also indicates the cadence of call
progress input. As DTMF signal lies in the same frequency band as
call progress signal, this pin may toggle for DTMF input. The SD pin
is at logic low in powerdown state.
Acknowledge Pulse Input.
After ESt or DStD is high, applying a
sequence of four pulses on this pin will then shift out four bits on the
SD pin, representing the decoded DTMF digit. The rising edge of the
first clock is used to latch the 4-bit data prior to shifting. This pin is
pulled down internally. The idle state of the ACK signal should be
low.
9
11
4
5
4
5
V
SS
SD
13
6
6
ACK
15
7
7
Early Steering Output.
A logic high on ESt indicates that a DTMF
(MT3x70B)
signal is present. ESt is at logic low in powerdown state.
Delayed Steering Output.
A logic high on DStD indicates that a
(MT3x71B)
valid DTMF digit has been detected. DStD is at logic low in
powerdown state.
DStD
ESt
18
8
8
V
DD
Positive Power Supply (5V Typ.)
Performance of the device can be
optimized by minimizing noise on the supply rails. Decoupling
capacitors across V
DD
and V
SS
are therefore recommended.
No Connection.
Pin is unconnected internally.
1,5,7,8,
10, 12,
14,16,
17
3
-
-
NC
-
2
PWDN
Power Down Input.
A logic high on this pin will power down the
device to reduce power consumption. This pin is pulled down
internally and can be left open if not used. ACK pin should be at logic
’0’ to power down device.
4-4
MITEL [ MITEL NETWORKS CORPORATION ]
