MT3170B/71B, MT3270B/71B, MT3370B/71B
MT3370B/71B
MT3170B/71B
MT3270B/71B
MT3370B/71B
20
1
2
3
4
5
6
7
8
NC
NC
VDD
NC
ESt/DStD
NC
ACK
SD
NC
NC
NC
NC
INPUT
PWDN
NC
OSC2
OSC1
VSS
NC
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
NC
INPUT
PWDN
OSC2
NC
VDD
NC
NC
ESt/DStD
NC
ACK
NC
19
18
17
16
15
14
13
12
11
INPUT
PWDN
CLK
VDD INPUT
VDD
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
ESt/
ESt/
DStD
OSC2
DStD
OSC1
VSS
ACK
SD
ACK
OSC1
NC
VSS
SD
NC
SD
NC
9
10
VSS
NC
8 PIN PLASTIC DIP
18 PIN PLASTIC SOIC
20 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
337xB
327xB
317xB
2
4
6
1
2
3
1
-
INPUT DTMF/CP Input. Input signal must be AC coupled via capacitor.
OSC2 Oscillator Output.
3
OSC1 Oscillator/Clock Input. This pin can either be driven by:
(CLK) 1) an external digital clock with defined input logic levels. OSC2
should be left open.
2) connecting a crystal or ceramic resonator between OSC1 and
OSC2 pins.
9
4
5
4
5
VSS
SD
Ground. (0V)
11
Serial Data/Call Progress Output. This pin serves the dual function
of being the serial data output when clock pulses are applied after
validation of DTMF signal, and also indicates the cadence of call
progress input. As DTMF signal lies in the same frequency band as
call progress signal, this pin may toggle for DTMF input. The SD pin
is at logic low in powerdown state.
13
15
18
6
7
6
7
ACK
Acknowledge Pulse Input. After ESt or DStD is high, applying a
sequence of four pulses on this pin will then shift out four bits on the
SD pin, representing the decoded DTMF digit. The rising edge of the
first clock is used to latch the 4-bit data prior to shifting. This pin is
pulled down internally. The idle state of the ACK signal should be
low.
ESt
(MT3x70B)
Early Steering Output. A logic high on ESt indicates that a DTMF
signal is present. ESt is at logic low in powerdown state.
Delayed Steering Output. A logic high on DStD indicates that a
valid DTMF digit has been detected. DStD is at logic low in
powerdown state.
DStD
(MT3x71B)
8
-
8
-
VDD
NC
Positive Power Supply (5V Typ.) Performance of the device can be
optimized by minimizing noise on the supply rails. Decoupling
capacitors across VDD and VSS are therefore recommended.
1,5,7,8,
10, 12,
14,16,
17
No Connection. Pin is unconnected internally.
3
-
2
PWDN Power Down Input. A logic high on this pin will power down the
device to reduce power consumption. This pin is pulled down
internally and can be left open if not used. ACK pin should be at logic
’0’ to power down device.
4-4
MITEL [ MITEL NETWORKS CORPORATION ]
