MH89790B
BIT
7
6
Preliminary Information
NAME
N/A
SiMUX
Keep at zero for normal operation.
DESCRIPTION
When set to ‘1’, this bit will cause the SMFI CRC result to be transmitted in the next outgoing Si1
bit in frame 13 and the SMFII CRC result to be transmitted in the next outgoing Si2 bit in frame
15.
Remote Loopback:
respectively.
If set the RxT and RxR signals are looped to OUTA and OUTB,
5
4
3
RMLOOP
HDB3en
Maint
Enable HDB3 Encoding:
A ’1’ will disable the HDB3 line coding and transmit the information
transparently.
Maintenance:
A ’1’ will force a complete reframe if the CRC multiframe synchro- nization is not
achieved within 8 ms of frame synchronization. Reframe will also be generated if more than 914
CRC errors occur within a one second interval (CRC error counter is reset with every one second
interval). A ’0’ will disable this option.
Enable Cyclical Redundancy Check:
A ’1’ will enable the CRC generation on the transmit
data. A ’0’ will disable the CRC generator. The CRC receiver is always active regardless of the
state of CRCen.
Digital Loopack:
When set, the transmitted signal is looped around from DSTi to DSTo. The
normal received data is interrupted.
Force Reframe:
If set, for at least one frame, and then cleared the chip will begin to search for a
new frame position when the chip detects the change in state from high to low. Only the change
from high to low will cause a reframe, not a continuous low level.
2
CRCen
1
0
DGLOOP
ReFR
Table 9. Master Control Word 3 (MCW3): Data Format for CSTi1 Channel 18
BIT
7-4
NAME
MA1-4
DESCRIPTION
Receive Multiframe Alignment Bits 1 to 4:
These are the bits which are received from the
CEPT 2048 kbit/s link in bit positions 1 to 4 of timeslot 16 of frame 0 of the multiframe. They
should all be ‘0‘.
This is the bit which is received on the CEPT 2048 kbit/s link in bit position 5 of timeslot 16 of
frame 0 of the multiframe. It is a spare bit which should be ‘1‘ if unused. It is not debounced.
This is the bit which is received on the CEPT 2048 kbit/s link in bit position 6 of timeslot 16 of
frame 0 of the multiframe. It is used to indicate the loss of multiframe alignment at the remote end
of the link. A ‘1‘ on this bit is the signal that multiframe alignment at the remote end of the link has
been lost. A ‘0‘ indicates that multiframe alignment is detected. It is not debounced.
These are the bits which are received on the CEPT 2048 kbit/s link in bit positions 7 and 8
respectively, of timeslot 16 of frame 0 of the multiframe. They are spare bits which should be ‘1‘ if
unused. They are not debounced.
3
2
X1
Y
1,0
X2,X3
Table 10. Received Multiframe Alignment Signal: Data Format for CSTo Channel 0
Control Input 1 (CSTi1)
Control ST-BUS input stream number 1 (CSTi1)
contains the synchronization information and the A,
B, C & D signalling bits for insertion into timeslot 16
of the CEPT stream (refer to Tables 5 to 8). Timeslot
0 contains the four zeros of the multiframe alignment
signal plus the XYXX bits (see Figure 4). Channels 1
to 15 of CSTi1 contain the A, B, C & D signalling bits
as defined by the CEPT format (see Figure 4), i.e.,
channel 1 of CSTi1 contains the A, B, C & D bits for
DSTi timeslots 1 and 17. Channel 16 contains the
frame alignment signal, and channel 17 contains the
non-frame alignment signal (see Figure 3). Channel
18 contains the Master Control Word 3 (see Table 9).
4-196
Figure 10 shows the relationship between the control
stream (CSTi1) and the CEPT stream.
Control Output (CSTo)
Control ST-BUS output (CSTo) contains the
multiframe signal from timeslot 16 of frame 0 (see
Table 10). Signalling bits, A, B, C & D for each CEPT
channel are sourced from timeslot 16 of frames 1-15
and are output in channels 1-15 on CSTo , as shown
in Table 11. The
frame alignment signal and
non-frame alignment signal, received from timeslot
0 of alternate frames are output in timeslots 16 and
17, as shown in Tables 12 and 13.
MITEL [ MITEL NETWORKS CORPORATION ]
