Preliminary Information
MH89770
T1 Interface
MH89770
Asynchronous
Interface
Protocol Converter
Switch Matrix
MT8980
ACIA
D -D
DSTi
STo1
STi1
STi0
OUTA
MT8952
•
Equal-
izer
DSTo
0
7
7
STo0
R
S
2
3
2
•
A -A
0
OUTB
RxT
CSTi0
CSTo
CSTi1
STo2
STi2
D -D
0
7
7
A -A
0
STo3
RxR
C2i
Micro
68008
ACIA
F0i
C4i
F0i
MT8952
D -D
0
A -A
0
7
7
•
•
C1.5i
R
S
2
3
2
E8Ko
•
•
D -D
0
7
7
•
•
A -A
•
•
0
MT8941
DPLL #1
ACIA
D -D
CVb
F0i
C1.5i
•
MT8952
R
0
7
7
C12i
DPLL #2
12.352
MHz
Osc.
S
2
3
2
A -A
0
•
D -D
F0b
F0i
0
7
7
•
C8Kb
A -A
0
C4b
C20
C4i
C2i
16.384
•
•
•
•
•
•
•
•
•
•
MHz
Osc.
•
•
•
Figure 16 - Digital Multiplex Interface (DMI)
The control block only interfaces with the switch
matrix. Besides routing channels and signalling
through to the proper destination, the switch matrix
must also supply the Master Control Words, and
monitor the Master Status Words for each MH89770.
transmit clock that is phase-locked to F0o, which in
turn is phase-locked to the master synchronization
signal, E8Ko. If all of the T1 trunks are from the
network any short term differences in the received
data rate will be absorbed by the elastic buffer in the
MH89770.
The clock generation block supplies the ST-BUS
clocks and the T1 transmit clocks that are
synchronized to one of the T1 trunks. All of the
extracted 8 kHz outputs are NANDed together before
they are input to PLL #2 of the MT8941.
6. Digital Multiplex Interface (DMI)
Figure 16 illustrates an implementation of the Digital
Multiplex Interface (DMI) specification, which defines
a computer to PBX interface. This interface can
convert 300 baud to 64 kbaud asynchronous or
synchronous data channels to T1 format with clear
channel capabilities and common channel signalling.
Phase-locked Loop #2 of the MT8941, will generate
ST-BUS clock signals for the MH89770s and the
MT8980s that are synchronized with the chosen T1
line. The E8Ko of all of the other MH89770s can be
tristated from the Master Control Word, which allows
the system controller to select any one of 128 T1
lines to act as the synchronization source. By
connecting the frame pulse output, F0o, of PLL #2 to
F0i of PLL # 1, the MT8941 will generate the T1
Figure 16 is broken down into four functional blocks
which are the asynchronous interface (ACIAs), the
protocol converter (micro and MT8952s), the switch
matrix (MT8980), and the T1 interface (MH89770).
4-147
MITEL [ MITEL NETWORKS CORPORATION ]
