Preliminary Information
Pin Description (Continued)
Pin #
17
18
Name
DSTi
C2i
Description
MH89760B
Data ST-BUS Input:
This pin accepts a 2048 kbit/s serial stream which contains the 24
PCM or data channels to be transmitted on the T1 trunk.
2.048 MHz System Clock (Input):
This is the master clock for the ST-BUS section of
the chip. All data on the ST-BUS is clocked in on the falling edge of C2i and out on the
rising edge.
1.544 MHz Extracted Clock (Output):
Internally connected to Pin 3.
Frame Pulse Input:
This is the frame synchronization signal which defines the
beginning of the 32 channel ST-BUS frame.
System ground.
No Connection.
Output A (Open Collector Output):
This is the output of the DS1 transmitter circuit. It is
suitable for use with an external pulse transformer to generate the transmit bipolar line
signal.
Transmit Superframe Pulse Input:
A low pulse applied at this pin will determine the
start of the next transmit superframe as illustrated in Figure 20. The device will free run if
this pin is held high.
Received Superframe Pulse Output:
A pulse output on this pin indicates that the next
frame of data on the ST-BUS is from frame 1 of the received superframe. The period is
12 frames long in D3/D4 modes and 24 frames in ESF mode. Active only when device is
synchronized to received DS1 signal.
1.544 MHz Clock Input:
The rising edge of this clock is used to output data on OUTA,
OUTB. C1.5i must be phase-locked to the C2i system clock.
Output B (Open Collector Output):
This is the output of the DS1 transmitter circuit. It is
suitable for use with an external pulse transformer to generate the transmit bipolar line
signal.
Received Facility Data Link (Output):
A 4 kbit/s serial output stream that is
demultiplexed from the FDL bits in ESF mode, or the received F
S
bit pattern when in
SLC96 mode. It is clocked out on the rising edge of RxFDLClk.
Data ST-BUS Output:
A 2048 kbit/s serial output stream which contains the 24 PCM or
data channels received from the DS1 line.
Receive Facility Data Link Clock Output:
A 4 kHz clock used to output FDL
information on RxFDL. Data is clocked out on the rising edge of the clock.
No Connection.
Transmit Facility Data Link Clock Output:
A 4 kHz clock used to input FDL
information on TxFDL. Data is clocked in on the rising edge of the clock.
No Connection.
Transmit Facility Data Link (Input)
:
A 4 kbit/s serial input stream that is muxed into the
FDL bits in the ESF mode, or the F
S
pattern when in SLC96 mode. It is clocked in on the
rising edge of TxFDLClk.
No Connection.
Loss of Signal (Output):
This pin goes high when 128 contiguous ZEROs are received
on the RxT and RxR inputs. When LOS is high, RxA and RxB are forced high. LOS is
reset when 48 ones are received in a two T1-frame period.
No Connection.
No Connection.
4-57
19
20
21
22-24
25
E1.5o
F0i
V
SS
NC
OUTA
26
TxSF
27
RxSF
28
29
C1.5i
OUTB
30
RxFDL
31
32
33
34
35
36
DSTo
RxFDLClk
V
SS
TxFDLClk
NC
TxFDL
37
38
NC
LOS
39
40
NC
NC
MITEL [ MITEL NETWORKS CORPORATION ]
