MEB90500
Advance Information
The MCEK also provides the customer with the
ability to use the following clock modes:
Functional Requirements
Interface and Mechanical - this evaluation kit offers
two PC-compatible boards with an ISA interface. The
boards are fitted with an MVIP 40-pin connector, one
RJ-11 jack for handset connection, and an optical
module connector for the ATM 155 connection.
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Adaptive
Freerun
Synchronized to the 155Mbps PHY device
(receive only)
Hardware
Note: For SYNC to PHY modes, the MCEK allows
the customer to access the 8kHz output from the
PHY chip.
Figure 1 outlines the physical characteristics of each
MT90500 Evaluation card available in the kit.
In addition, this kit contains a software algorithm for
an adaptive clock recovery method.
The evaluation board is a PC-compatible 8/16-bit ISA
board which provides the following interfaces:
In regards to clock generation and recovery, the
cards can either generate clocks in master mode or
receive input clocks in slave mode.
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ATM155 MMF optical interface (ATM)
MVIP compatibility (TDM)
Handset Connector (Local TDM)
Software, Device Drivers
The specific components used are shown in Figure
1. The FPGA module emulates a Motorola/Intel
processor via the ISA bus interface. This module
emulates the functionality of a µprocessor and
integrates all the other logic functions that are
required to operate the board. It provides the
necessary control for the operation of the Mitel
codec (MT9160), LDX (MT90820) and external PLL
(MT9041) as required.
Three software modules are provided:
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A demonstration program which allows audio
communications between two cards connected
back to back via an ATM crossover cable or an
ATM switch. The audio communication will be
provided on each card via a telephone handset
(codec on local bus). The software
The Mitel MT90820 LDX device allows the user to
generate 64 kbps or nx64 kbps patterns to the
MT90500 device, at 2.048, 4.096 and 8.192 Mbps.
demonstrates how to set up one channel per
VC in structured data transfer (SDT) mode. The
clock mode (one of the 3 mentioned above) can
be selected by the user. This demonstration
program also allows the user to configure the
MT90500 for multiple channels per VC in
structured data transfer (SDT) mode or pointer-
free mode, including the option for the clock
mode selection. The pertinent documented C
source code for this demo software is provided.
This software runs under Windows NT.
A demonstration program showing the power of
the MT90500. To accomplish this objective, the
application transmits 1024 channels
simultaneously. The pertinent documented C
source code for this demonstration is provided.
The driver initializes the card, including the
FPGA.
A diagnostic module which provides access to
registers within the Mitel MT90500 and its
external memory. The diagnostic software is
able to run while the other software is
The card contains an MT9160 codec interfacing with
a telephone handset for demo purposes. A GUI
interface is provided to operate the codec.
The MCEK is provided with two Synchronous SRAM
(64K x 18) used by the MT90500 to externally store
its control and data structures.
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The MCEK is built with the tools necessary to
exercise directly most of the MT90500 functionality:
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µprocessor interface (headers on control
signals)
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external SSRAM interface
TDM interface (external via the MVIP
connector; local via headers)
UTOPIA interface (primary and auxiliary
interface headers)
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operating. This software runs under Windows
NT.
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JTAG port (headers)
TDM clock recovery and generation
2
MITEL [ MITEL NETWORKS CORPORATION ]
