ACE9030
Radio Interface Bus - Transmit
TheACE9030onlydrivesthebusinresponsetoarequest
for data by a Normal command as described above. To avoid
any bus contention, there is a delay from the end of a data
requesttothestartoftheresponse,seefigure10.Thedatawill
start on the fifth rising edge of CL after the rising edge of
LATCHB.
The output Preamble word begins with a fixed pattern
1 0 1 0andthenincludesthesourcecodenumber(Y1, Y0)for
the Result words and the status of the Lock Detect from the
synthesiser, all as described in the section Polling A to D
Converter.
CL
1
2 3 4 5
PREAMBLE
RESULT1
RESULT2
DATA3
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7 6 5 4 3 2 1 0
LATCHB
Fig.10 Radio Interface transmit bus timing
Synthesiser Bus - Receive Only
The overall format to control the synthesiser is basically the
same as for the Radio Interface. There is an option of a 32 bit
sequence for the A word. The width of the LATCHC pulse is
used to set the duration of speed-up mode when changing
channels.
CL
DATA (WORD A)
N2
NF
N1
0
1
7
6
0
5
4
3
2
2
1
0 11 10 9
8
7
6
5
4
3
3
3
3
3
2
1 0
2
0
1
0
0
0
DATA (WORD B)
DATA (WORD C)
L
CN
TEST
0
K
1
0
3
1
0
7
6
5
4
3
7
7
7
2
1
0
2
2
1
1
0
0
0
0
not used
DM
1
0
0
1
0
0
1
1
11 10
9
8
8
8
6
5
4
4
LG DA
FMOD
DM
DATA (WORD D)
DATA (WORD A2)
NR
5
SA
SM
0 11 10
1
0
1
9
6
2 1
N2
N1
NF
1
CN
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0 11 10 9
6
5
4
2
1
2
0
LATCHC
DURATION OF MAIN SYNTHESISER SPEED-UP MODE
DATA (DUMMY WORD)
- ONLY USED TO ALLOW
1
1 1 1
not used - any data may fill space
LATCHC TO REMAIN HIGH
Fig.11 Synthesiser bus timing
13
MITEL [ MITEL NETWORKS CORPORATION ]
