ACE9030
Radio Interface Bus - Transmit
The ACE9030 only drives the bus in response to a request
for data by a Normal command as described above. To avoid
any bus contention, there is a delay from the end of a data
request to the start of the response, see figure 10. The data will
start on the fifth rising edge of CL after the rising edge of
LATCHB.
The output Preamble word begins with a fixed pattern
1 0 1 0 and then includes the source code number (Y1, Y0) for
the Result words and the status of the Lock Detect from the
synthesiser, all as described in the section Polling A to D
Converter.
CL
1 2 3 4 5
DATA3
PREAMBLE
7 6 5 4 3 2 1 0
LATCHB
RESULT1
7 6 5 4 3 2 1 0
RESULT2
7 6 5 4 3 2 1 0
Fig.10 Radio Interface transmit bus timing
Synthesiser Bus - Receive Only
The overall format to control the synthesiser is basically the
same as for the Radio Interface. There is an option of a 32 bit
sequence for the A word. The width of the LATCHC pulse is
used to set the duration of speed-up mode when changing
channels.
CL
DATA (WORD A)
N2
N1
3 2 1 0
TEST
2 1 0
NF
2 1 0
0
7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4
DATA (WORD B)
0 0
L
K
CN
0 0 0 1
1 0 3 2 1 0 7 6 5
DATA (WORD C)
not used
4 3 2 1 0 3
DM
1 0 0 1
2 1 0
0 1 0 1
0
NF
D
11 10 9 8 7 6 5 4 3
LG
DATA (WORD D)
DA
SA
FMOD 1 0
DATA (WORD A2)
CN
7 6 5 4 3 2 1 0 7
LATCHC
N2
6 5 4 3 2 1 0 11 10 9 8 7
N1
DM
SM
NR
1 0 11 10 9 8 7 6 5 4 3 2 1
6 5 4 3 2 1 0 2 1 0
DURATION OF MAIN SYNTHESISER SPEED-UP MODE
DATA (DUMMY WORD)
- ONLY USED TO ALLOW
LATCHC TO REMAIN HIGH
not used - any data may fill space
1 1 1 1
Fig.11 Synthesiser bus timing
13
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